29 June 2012 EUV and 193 mask line width roughness (LWR) impact on wafer CD LWR
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Proceedings Volume 8441, Photomask and Next-Generation Lithography Mask Technology XIX; 84410V (2012) https://doi.org/10.1117/12.964397
Event: Photomask and NGL Mask Technology XIX, 2012, Yokohama, Japan
Abstract
Influence of the mask error becomes serious because of the shrinkage of device pitch. The impact of mask line width roughness (LWR) on wafer CD needs to be studied on advanced node, because the device performance of semiconductor will be impacted seriously by wafer LWR/LER (line edge roughness). The Gate line width variation is a critical issue on advanced nodes. In this paper, we evaluate the LWR relationship between mask and wafer. We start the mask and wafer LWR study by simulation (aerial image model, and resist model) to see whether simulation meets optical theory. Besides, we also confirm the wafer printing result to compare simulation and wafer performance. Based on our study, simulation and wafer data show that the mask LWR has no obvious impact on wafer LWR even if on EUV (13.5nm wavelength) process.
© (2012) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Chain Ting Huang, Chain Ting Huang, Cloud Cheng, Cloud Cheng, Ming Jui Chen, Ming Jui Chen, } "EUV and 193 mask line width roughness (LWR) impact on wafer CD LWR", Proc. SPIE 8441, Photomask and Next-Generation Lithography Mask Technology XIX, 84410V (29 June 2012); doi: 10.1117/12.964397; https://doi.org/10.1117/12.964397
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