15 October 2012 An FPGA architecture for MPEG-2 TS demultiplexer
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Proceedings Volume 8454, Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2012; 84540W (2012) https://doi.org/10.1117/12.2000181
Event: Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2012, 2012, Wilga, Poland
Abstract
This paper presents a novel architecture of a MPEG-2 TS demultiplexer, implemented with a FPGA. The main objective of the design is an ability to separate selected elementary streams in real time, while ensuring minimal resource consumption. This is achieved by the decomposition of the demultiplexer into a number of independent sub-modules, which process the data in parallel. The flexible structure enables adaptation to the specific needs and significantly simplifies potential expansion, what may be important due to a wide range of potential applications of the MPEG-2 TS standard. To improve the functionality, the demultiplexer is equipped with a configuration and status interface. The transport stream and configuration data are supplied to the FPGA by a microcontroller through the External Peripheral Interface (EPI). The data is transmitted to the microcontroller via Ethernet, using the User Datagram Protocol (UDP).
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Andrzej Abramowski, Andrzej Abramowski, } "An FPGA architecture for MPEG-2 TS demultiplexer", Proc. SPIE 8454, Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2012, 84540W (15 October 2012); doi: 10.1117/12.2000181; https://doi.org/10.1117/12.2000181
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