15 October 2012 Performance of a 512 x 512 gated CMOS imager with a 250 ps exposure time
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Abstract
We describe the performance of a 512x512 gated CMOS read out integrated circuit (ROIC) with a 250 ps exposure time. A low-skew, H-tree trigger distribution system is used to locally generate individual pixel gates in each 8x8 neighborhood of the ROIC. The temporal width of the gate is voltage controlled and user selectable via a precision potentiometer. The gating implementation was first validated in optical tests of a 64x64 pixel prototype ROIC developed as a proof-of-concept during the early phases of the development program. The layout of the H-Tree addresses each quadrant of the ROIC independently and admits operation of the ROIC in two modes. If “common mode” triggering is used, the camera provides a single 512x512 image. If independent triggers are used, the camera can provide up to four 256x256 images with a frame separation set by the trigger intervals. The ROIC design includes small (sub-pixel) optical photodiode structures to allow test and characterization of the ROIC using optical sources prior to bump bonding. Reported test results were obtained using short pulse, second harmonic Ti:Sapphire laser systems operating at λ~ 400 nm at sub-ps pulse widths.
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Alan T. Teruya, Stephen P. Vernon, James D. Moody, Warren W. Hsing, Christopher G. Brown, Matthew Griffin, Andrew S. Mead, Vu Tran, "Performance of a 512 x 512 gated CMOS imager with a 250 ps exposure time", Proc. SPIE 8505, Target Diagnostics Physics and Engineering for Inertial Confinement Fusion, 85050F (15 October 2012); doi: 10.1117/12.930150; https://doi.org/10.1117/12.930150
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