19 October 2012 Onboard optimized hardware implementation of JPEG-LS encoder based on FPGA
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A novel hardware implementation of JPEG-LS Encoder based on FPGA is introduced in this paper. Using a look-ahead technique, the critical delay paths of LOCO-I algorithm, such as feedback-loop circuit of parameters updating, are improved. Then an optimized architecture of JPEG-LS Encoder is proposed. Especially, run-mode encode process of JPEG-LS is covered in the architecture as well. Experiment results show that the circuit complexity and memory consumption of the proposed structure are much lower, while the data processing speed is much higher than some other available structures. So it is very suited for applying high-speed lossless compression of satellite sensing image onboard.
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Wen Wei, Wen Wei, Jie Lei, Jie Lei, Yunsong Li, Yunsong Li, } "Onboard optimized hardware implementation of JPEG-LS encoder based on FPGA", Proc. SPIE 8514, Satellite Data Compression, Communications, and Processing VIII, 851406 (19 October 2012); doi: 10.1117/12.930869; https://doi.org/10.1117/12.930869

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