To continue scaling the circuit features down, Double Patterning (DP) technology is needed in 22nm technologies and
lower. DP requires decomposing the layout features into two masks for pitch relaxation, such that the spacing between
any two features on each mask is greater than the minimum allowed mask spacing. The relaxed pitches of each mask are
then processed on two separate exposure steps. In many cases, post-layout decomposition fails to decompose the layout
into two masks due to the presence of conflicts.
Post-layout decomposition of a standard cells block can result in native conflicts inside the cells (internal conflict), or
native conflicts on the boundary between two cells (boundary conflict). Resolving native conflicts requires a redesign
and/or multiple iterations for the placement and routing phases to get a clean decomposition. Therefore, DP compliance
must be considered in earlier phases, before getting the final placed cell block.
The main focus of this paper is generating a library of decomposed standard cells to be used in a DP-aware placer. This
library should contain all possible decompositions for each standard cell, i.e., these decompositions consider all possible
combinations of boundary conditions. However, the large number of combinations of boundary conditions for each
standard cell will significantly increase the processing time and effort required to obtain all possible decompositions.
Therefore, an efficient methodology is required to reduce this large number of combinations. In this paper, three different
reduction methodologies are proposed to reduce the number of different combinations processed to get the decomposed
library. Experimental results show a significant reduction in the number of combinations and decompositions needed for
the library processing. To generate and verify the proposed flow and methodologies, a prototype for a placement-aware
DP-ready cell-library is developed with an optimized number of cell views.