This paper provides DFM solutions on yield improvement based on a foundry’s perspective. We have created a
novel work flow for efficient yield enhancement at different stages throughout the process of design-to-silicon. In
the design environment, other than conforming to the conventional design rule manual, we may guide the designer
to employ the well-characterized regular logic bricks that are built from process validated hotspots. Later, after
design sign-off, layout manipulation or layout retargeting are implemented during the mask preparation stage to
enlarge the process window when faced with a diversity of layout patterns in the design. At the same time, two
crucial methods, namely layout analysis and layout comparison, are used to capture all layout related detractors. The
first method can identify the process sensitive hotspots, which will be highlighted and anchored as process limiters
during the patterning process. Layout comparison can be an efficient way to narrow down the yield roadblocks by
debugging the yield loss on similar process and design styles. Another smart solution is creating customized process
control monitoring structures (PCM), which are extracted from previous yield ramping lessons and process hotspots.
These PCMs will be dropped into scribe lane of production tapeouts and serve as pioneer testkeys for the initial
production ramp up.