15 October 2012 Semi-analytical estimation of intra-die variations of analog performances of nano-scale nMOS transistor
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Proceedings Volume 8549, 16th International Workshop on Physics of Semiconductor Devices; 854904 (2012) https://doi.org/10.1117/12.925339
Event: 16th International Workshop on Physics of Semiconductor Devices, 2011, Kanpur, India
Abstract
This paper presents a semi analytical technique for estimating the effects of intra-die process variations on the performances of an nMOS transistor. The intra-die process variability sources considered in the work are Random Discrete Dopants (RDD), Channel Length Variation (CLV), Oxide Thickness Variation (OTV) and Mobility Fluctuation (MF). The analog performances which are studied are transconductance gm, intrinsic speed ft , thermal noise spectral density Sn and flicker noise spectral density Sf. The estimation technique is based on BSIMIV-SPICE process parameters. The mean and standard deviation of the performance variations are estimated. The estimated results are verified through Monte Carlo (MC)-HSPICE simulation results.
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Sarmista Sengupta, Sarmista Sengupta, Soumya Pandit, Soumya Pandit, } "Semi-analytical estimation of intra-die variations of analog performances of nano-scale nMOS transistor", Proc. SPIE 8549, 16th International Workshop on Physics of Semiconductor Devices, 854904 (15 October 2012); doi: 10.1117/12.925339; https://doi.org/10.1117/12.925339
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