15 October 2012 0.4μm high voltage CMOS smart power technology: 120V LD NMOS for integrated system on chip applications
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Proceedings Volume 8549, 16th International Workshop on Physics of Semiconductor Devices; 85490R (2012) https://doi.org/10.1117/12.926994
Event: 16th International Workshop on Physics of Semiconductor Devices, 2011, Kanpur, India
Abstract
In this work, we demonstrate best in class 120V Lateral Drain NMOS devices using 0.4um CMOS technology. These devices are fabricated with just 1 additional mask to the baseline CMOS process flow. 2D TCAD simulations were first carried out to identify the device with best breakdown voltage (BVdss) and specific on resistance (Rsp) combination. Then, a Design of Experiment (DOE) in layout was carried out around the best simulated device for different geometries (channel, Drain Extension and Field plate lengths). Rsp as low as 244 mohm-mm2 is achieved for a BVdss of 177V. This is more than 35% improvement over the best device reported in the industry so far [1]. Increasing channel length helps in improving the full bias stability of the device, albeit at the cost of Rsp. However, Rsp still remains lower than present industry state of the art.
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Nayan Patel, "0.4μm high voltage CMOS smart power technology: 120V LD NMOS for integrated system on chip applications", Proc. SPIE 8549, 16th International Workshop on Physics of Semiconductor Devices, 85490R (15 October 2012); doi: 10.1117/12.926994; https://doi.org/10.1117/12.926994
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