5 December 2012 A low-power SAR ADC for IRFPA ROIC
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This paper presents a low power ADC for the 512*512 infrared focal plane arrays (IRFPA) readout integrated circuit(ROIC). The major structure, the working mode and the simulation result of the readout integrated circuit are shown in this paper. The power supply voltage of 0.35μm standard CMOS process is 3.3V in this design, and then the output range of the Direct Injection (DI) input circuit is reached 2V. Successive-approximation-register (SAR) ADC architecture is used in this readout integrated circuit. And each ADC is shared by one column of the IRFPA. This SAR ADC is made up of a 13-bit digital-analog converter (DAC), a high resolution comparator, and a digital control circuit. The most important part is the voltage-scaling and charge-scaling charge redistribution DAC. In this DAC, charge scaling with a capacitor ladder to determine the least significant bits is combined with voltage scaling with a resister ladder to determine the most significant bits. The comparator uses three-stage operational amplifier structure to get a 77dB differential gain. The Common-Mode input rang of the comparator is 1V to 3V, and minimum resolvable voltage difference is 0.3mV. This SAR ADC has some advantages, especially in low power and high speed. The simulation result shows that the resolution of the ADC is 12 bit and the conversion time of the ADC is 6.5μs, while the power of each ADC is as low as 300μW. Finally, this SAR ADC can satisfy the request of 512*512 IRFPAs ROIC with a 100Hz frame rate.
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Lei Gao, Ruijun Ding, Jie Zhou, Pan Wang, Guoqiang Chen, "A low-power SAR ADC for IRFPA ROIC", Proc. SPIE 8562, Infrared, Millimeter-Wave, and Terahertz Technologies II, 856210 (5 December 2012); doi: 10.1117/12.981856; https://doi.org/10.1117/12.981856

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