4 March 2013 Optimization of the hybrid silicon photonic integrated circuit platform
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Proceedings Volume 8640, Novel In-Plane Semiconductor Lasers XII; 86400U (2013) https://doi.org/10.1117/12.2002967
Event: SPIE OPTO, 2013, San Francisco, California, United States
Abstract
In the hybrid silicon platform, active III/V based components are integrated on a silicon-on-insulator photonic integrated circuit by means of wafer bonding. This is done in a self-aligned back-end process at low temperatures, making it compatible with CMOS-based silicon processing. This approach allows for low cost, high volume, high quality and reproducible chip fabrication. Such features make the hybrid silicon platform an attractive technology for applications like optical interconnects, microwave photonics and sensors operating at wavelengths around 1.3 μm and 1.55 μm. For these applications energy efficient operation is a key parameter. In this paper we present our efforts to bring the III/V components in the hybrid silicon platform, such as lasers and optical amplifiers, on par with the far more mature monolithic InP-based integration technology. We present our development work to increase hybrid silicon laser and amplifier wall-plug efficiency. This is done by careful optimization of III/V mesa geometry and guiding silicon waveguide width. We also discuss current injection efficiency and thermal performance. Furthermore we show the characterization of the low-loss and low-reflection mode converters that couple the hybrid III/V components to silicon waveguides. Reflections below -41 dB and passive loss of 0.3 dB per converter were obtained.
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Martijn J. R. Heck, Michael L. Davenport, Sudharsanan Srinivasan, Jared Hulme, John E. Bowers, "Optimization of the hybrid silicon photonic integrated circuit platform", Proc. SPIE 8640, Novel In-Plane Semiconductor Lasers XII, 86400U (4 March 2013); doi: 10.1117/12.2002967; https://doi.org/10.1117/12.2002967
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