Paper
1 April 2013 Simulation-assisted layout biasing in EUV lithography and prediction of an optimum resist parameter space
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Abstract
This paper demonstrates a new simulation-based methodology for optimizing critical dimension (CD) bias for contact holes (CH) arrays using several different extreme ultraviolet (EUV) resists that were fully calibrated and verified with physical resist models. The bias for CH was optimized using local CD uniformity (CDU) 3-sigma as a cost function. The CD sigma variations of near-neighbor contact holes were simulated as a function of dose-to-size and mask bias, averaged over a large number of stochastic trials. There is a distinct bias for minimum CD sigma accompanied by an increase in the process window. The results are confirmed with wafer data. We will discuss the results in terms of EUV photon shot noise coupled with resist parameters. The simulation results will be used to predict a parameter space for EUV resist that can optimize line edge roughness (LER)/resolution/process window and CDU. Finally, various tradeoffs will be presented that will enable the process to perform in a high volume manufacturing environment.
© (2013) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Chandra Sarma, John Biafore, Kyoungyong Cho, Karen Petrillo, and Mark Neisser "Simulation-assisted layout biasing in EUV lithography and prediction of an optimum resist parameter space", Proc. SPIE 8679, Extreme Ultraviolet (EUV) Lithography IV, 86792U (1 April 2013); https://doi.org/10.1117/12.2011880
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Cited by 1 scholarly publication and 1 patent.
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KEYWORDS
Critical dimension metrology

Nanoimprint lithography

Extreme ultraviolet

Photomasks

Semiconducting wafers

Extreme ultraviolet lithography

Stochastic processes

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