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26 March 2013 Defect reduction for semiconductor memory applications using jet and flash imprint lithography
Zhengmao Ye, Kang Luo, J. W. Irving, Xiaoming Lu, Wei Zhang, Brian Fletcher, Weijun Liu, Matt Shafran, Saul Lee, Whitney Longsine, Van Truskett, Frank Xu, Dwayne LaBrake, Douglas Resnick, S. V. Sreenivasan
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Proceedings Volume 8680, Alternative Lithographic Technologies V; 86800C (2013) https://doi.org/10.1117/12.2013694
Event: SPIE Advanced Lithography, 2013, San Jose, California, United States
Abstract
Imprint lithography has been shown to be an effective technique for replication of nano-scale features. Jet and Flash Imprint Lithography (J-FIL) involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed leaving a patterned resist on the substrate. Acceptance of imprint lithography for manufacturing will require demonstration that it can attain defect levels commensurate with the defect specifications of high end memory devices. Typical defectivity targets are on the order of 0.10/cm2. In previous studies, we have focused on defects such as random non-fill defects occurring during the resist filling process and repeater defects caused by interactions with particles on the substrate. In this work, we attempted to identify the critical imprint defect types using a mask with NAND Flash-like patterns at dimensions as small as 26nm. The two key defect types identified were line break defects induced by small particulates and airborne contaminants which result in local adhesion failure. After identification, the root cause of the defect was determined, and corrective measures were taken to either eliminate or reduce the defect source. As a result, we have been able to reduce defectivity levels by more than three orders of magnitude in only 12 months and are now achieving defectivity adders as small as 2 adders per lot of wafers.
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Zhengmao Ye, Zhengmao Ye, Kang Luo, Kang Luo, J. W. Irving, J. W. Irving, Xiaoming Lu, Xiaoming Lu, Wei Zhang, Wei Zhang, Brian Fletcher, Brian Fletcher, Weijun Liu, Weijun Liu, Matt Shafran, Matt Shafran, Saul Lee, Saul Lee, Whitney Longsine, Whitney Longsine, Van Truskett, Van Truskett, Frank Xu, Frank Xu, Dwayne LaBrake, Dwayne LaBrake, Douglas Resnick, Douglas Resnick, S. V. Sreenivasan, S. V. Sreenivasan, "Defect reduction for semiconductor memory applications using jet and flash imprint lithography", Proc. SPIE 8680, Alternative Lithographic Technologies V, 86800C (26 March 2013); doi: 10.1117/12.2013694; https://doi.org/10.1117/12.2013694
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