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So far, the CMOS technology roadmap has been consistent with Moore’s law, even if manufacturing photolithography
tools are now operating beyond their resolution limit. This has been made feasible at the expense of an intensive joint
work between designers and process people who have successfully enabled double patterning processes. Tools that can
provide photo lithographers with some relief are on their way although not yet in production. Among them, massively
parallel mask-less electron beam lithography stands out as a serious candidate since it can achieve the required resolution
at the right cost of ownership provided targeted throughput performance is reached. This paper focuses on this latter
technique and more precisely, reports on simulation works performed using an emulator of the high volume
manufacturing tool being developed by MAPPER Lithography, called MATRIX.
In a nutshell, the MATRIX tool will operate using more than 13,000 beams, each one writing a stripe 2μm wide. Each
beam itself will be composed of 49 individual sub-beams that can be blanked independently in order to write pixels onto
the wafer. The residual placement errors and any current mismatch between the beams will be measured in-situ and
corrected through the data path. In order to validate that this concept can actually work, the authors have built an off-line
emulator of the data treatment performed down to the information sent to the blanker. It has then been plugged into an
electron beam simulator such that the performance on real designs can be tested.
In this paper, the methodology used for the corrections is explained as well as the validation process applied. The results
of an extensive statistical study are presented showing CD, placement and residual scaling errors simulated on a set of
predefined key structures assuming current and misplacement ranges within the MATRIX tool specifications, applying
various correction solutions.
Based on the collected data, it is shown that CD uniformity on the MATRIX tool is better than +/-10% 3σ taking into
account data path, beam variation, stitching and shot noise effects, meeting specifications for circuits designed at 64nm pitch.
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