26 March 2013 Sub-22 nm silicon template nanofabrication by advanced spacer patterning technique for NIL applications
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Abstract
A spacer patterning technique using a poly-Si micro-feature and a SiO2 spacer has been demonstrated to achieve sub-22 nm structures with conventional semiconductor equipments. The sub-22 nm structures have been fabricated by a plasma etching of Si substrate with a spacer oxide mask of which dimension is accurately controlled by the deposited film thickness. The profile of the Si nano-feature was influenced by an O2 flow rate during Si etching in inductively coupled plasma (ICP). As the O2 flow rate was decreased, the etch profile was improved vertically even though the etch rate of Si was slightly decreased. We obtained a 6-inch Si template with both nano- and micro-features of positive shape used for a master mold in nanoimprint lithography (NIL). The nano-sized Si features showed 22-nm width and 145-nm height with the slope of 87°. Further size reduction by anisotropic wet etching with KOH solution was also investigated.
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Jong-Moon Park, Kun-Sik Park, Dong-Pyo Kim, Seong-Ook Yoo, Jin-Ho Lee, "Sub-22 nm silicon template nanofabrication by advanced spacer patterning technique for NIL applications", Proc. SPIE 8680, Alternative Lithographic Technologies V, 86802B (26 March 2013); doi: 10.1117/12.2011400; https://doi.org/10.1117/12.2011400
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