This PDF file contains the front matter associated with SPIE Proceedings Volume 8681, including the Title Page, Copyright Information, Table of Contents, and the Conference Committee listing.

Variations in key device parameters such as gate width, fin height, and storage node aspect ratio can lead to performance variations device to device and within die. Extreme excursions can result in yield loss. Metrology and process control are enablers to detect and keep these variations to within certain bounds. As the features of devices continue to shrink, the allowable tolerances for critical dimensions and overlay errors likewise must shrink, in turn forcing the metrology budgets to shrink in step. At the same time, more data is required per wafer to generate higher order analyses while at the same time greater productivity in terms of silicon area processed in unit time is needed to keep the economics favorable. It is essential we develop the strategies needed for metrology in times of shrinking budgets.

Metrology tools are increasingly challenged by the continuing decrease in the device dimensions, combined with complex disruptive materials and architectures. These demands are not being met appropriately by existing/forthcoming metrology techniques individually. Hybrid Metrology (HM) – the practice to combine measurements from multiple toolset types in order to enable or improve the measurement of one or more critical parameters – is being incorporated by the industry to resolve these challenges. Continuing our previous work we now take the HM from the lab into the fab. This paper presents the first-in-industry implementation of HM within a High Volume Manufacturing (HVM) environment. Advanced 3D applications are the first to use HM: 20nm Contact etch and 14nm FinFET poly etch. The concept and main components of this Phase-1 Host-based implementation are discussed. We show examples of communication protocols/standards that have been specially constructed for HM for sharing data between the metrology tools and fab host in GLOBALFOUNDRIES, as well as the HM recipe setup and HVM results. Finally we discuss our vision and phased progression/roadmap for Phase-2 HM implementation to fully reap the benefits of hybridization.

Aggressive on-product overlay requirements in advanced nodes are setting a superior challenge for the semiconductor industry. This forces the industry to look beyond the traditional way-of-working and invest in several new technologies. Integrated metrology², in-chip overlay control, advanced sampling and process correction-mechanism (using the highest order of correction possible with scanner interface today), are a few of such technologies considered in this publication.

The continuous need for lithography overlay performance improvement is a key point for advanced integrated circuit manufacturing. Overlay control is more and more challenging in the 2x nm process nodes regarding functionality margin of the chip and tool capability. Transistor architecture rules which are set, confirm poly to contact space as the most critical one for 28nm technology node. Critical Dimension variability of these layers, even with best in class process stability, in addition to design constraint lead to on product overlay specifications of around 7nm. In order to ensure that the target is met in production environment and to identify potential ways for improvement, identification of the contributors to overlay errors is essential. We have introduced a novel budget breakdown methodology using both bottom-up and top-down overlay data. For the bottom up part, we have performed extensive testing with very high sampling scheme so as to quantify the main effects. In-line overlay metrology data has been used for top down approach to verify the overall performance in production. In this paper we focused on the 28nm contact to gate overlay in a FDSOI process. The initial inconsistency between bottom up and top down results led us to further exploration of the root cause of these inconsistencies. We have been able to highlight key figures to focus on, like reticle heating, wafer table contamination and etch processing effects. Finally, we conclude on 7nm overlay target achievement feasibility in high volume manufacturing environment.

To fulfil advanced process control requirements for 1X node production, the semiconductor industry must cope with multiple parallel metrology requirements such as resolution, precision and accuracy enhancement in all directions to answer to new 3D integrated circuit fabrication methods. At the 1D and 2D levels, CDSEM and Scatterometry techniques are the workhorse techniques for production and process control. However, for process control of 3D devices and high resolution patterning such as direct self-assembly lithography, reference metrology is necessary to maintain a global process control uncertainty that is sufficient for production standards. CD-SEM and Scatterometry have intrinsic limitations that limit their utility for these cases, and new characterization methods are needed. Among the industrial reference techniques currently available, TEM and CD-AFM are generally employed to address this issues but both of these techniques have their own limitations for 1X node production. Nevertheless, they are also very useful for engineers to calibrate production CD metrology techniques and for more accurate process window and process development definition at the R&D level. Thus, there is a critical need to develop new technologies that build upon these capabilities while overcoming the limitations.

The automated metrology capabilities of a STEM using a commercially available 22nm microprocessor were evaluated. Artifact-free TEM samples with a thickness of 10-15nm were prepared from inverter structures at various locations within an SRAM array. Static and dynamic precision measurements made on fin and gate stack features show sub-nm precision, suggesting that fully automated STEM metrology on finFET devices is capable of supporting finFET production. This paper also discusses sample preparation, automated data acquisition and data analysis, as well as the throughput benefits that arise from hardware connectivity between the sample prep and data acquisition tools. Simultaneous STEM imaging and compositional analysis is also briefly discussed.

The Critical Dimension Scanning Electron Microscope (CDSEM) is the traditional workhorse solution for inline process control. Measurements are extracted from top-down images based on secondary electron collection while scanning the specimen. Secondary electrons holding majority of detection yield. These images provide more on the structural information of the specimen surface and less in terms of material contrast. In some cases there is too much structural information in the image which can irritate the measurement, in other cases small but important differences between various material compounds cannot be detected as images are limited by contrast information and resolution of primary scanning beam. Furthermore, accuracy in secondary electron based metrology is limited by charging. To gather the exact required information for certain material compound as needed, a technique, known from material analytic SEM´s has been introduced for inline CDSEM analysis and process control: Low Loss Back Scattered Electron Imaging (LL-BSE). The key at LL-BSE imaging is the collection of only the back scattered electrons (BSE) from outermost specimen surface which undergo the least amount possible of energy loss in the process of image generation following impact of the material by a primary beam. In LL-BSE very good and measurable material distinction and sensitivity, even for very low density material compounds can be achieved. This paper presents new methods for faster process development cycle, at reduced cost, based on LL-BSE mass data mining instead of sending wafers for destructive material analysis.

Traditional control of critical dimensions (CD) on photolithographic masks considers the CD average and a measure for the CD variation such as the CD range or the standard deviation. Also systematic CD deviations from the mean such as CD signatures are subject to the control. These measures are valid for mask quality verification as long as patterns across a mask exhibit only size variations and no shape variation. The issue of shape variations becomes especially important in the context of contact holes on EUV masks. For EUV masks the CD error budget is much smaller than for standard optical masks. This means that small deviations from the contact shape can impact EUV waver prints in the sense that contact shape deformations induce asymmetric bridging phenomena. In this paper we present a detailed study of contact shape variations based on regular product data. Two data sets are analyzed: 1) contacts of varying target size and 2) a regularly spaced field of contacts. Here, the methods of statistical shape analysis are used to analyze CD SEM generated contour data. We demonstrate that contacts on photolithographic masks do not only show size variations but exhibit also pronounced nontrivial shape variations. In our data sets we find pronounced shape variations which can be interpreted as asymmetrical shape squeezing and contact rounding. Thus we demonstrate the limitations of classic CD measures for describing the feature variations on masks. Furthermore we show how the methods of statistical shape analysis can be used for quantifying the contour variations thus paving the way to a new understanding of mask linearity and its specification.

We have succeeded in quantifying changes in 2D pattern shape, which are induced by exposure condition and Optical Proximity Correction (OPC), from CD-SEM image. In the current lithography technology, micro patterns which are close to resolution limit are printed on wafer by fully utilizing aggressive OPC technology. In such lithography technology, controlling the shape of printed patterns is extremely difficult. In order to control such difficult patterning process, a demand to precisely quantify the pattern shape of 2D patterns is significantly growing. SEM images captured by CD-SEM are used mainly for the measurement of one dimensional size such as line width and contact hole diameter. It has been said not easy to measure shape variation of 2D patterns such as corner and line end from SEM images. However, we have succeeded in quantifying pattern shape of 2D pattern by utilizing Advanced SEM contouring technology which is combined with CD-gap-free contouring technology [1] and Fine SEM Edge (FSE) technology [2]. By this, we could quantitatively measure shape variation which are induced by exposure condition variability and/ or OPC, which used to be considered difficult to quantify. For the verification of this new measurement technology, wafers on which printed 2D patterns that are exposed in different conditions and with varied SRAF changed in size and position are prepared. The 2D patterns are measured by CD-SEM and SEM images of the 2D patterns are taken. To the SEM images of the 2D patterns, this new measurement technology is applied to quantitatively analyze how the expose condition and SRAF variation affect the printed 2D pattern shape. In this paper, the results of above experiments are reported.

The impact on yield loss due to systematic defect which remains after Optical Proximity Correction (OPC) modeling has increased, and achieving an acceptable yield has become more difficult in the leading technology beyond 20 nm node production. Furthermore Process-Window has become narrow because of the complexity of IC design and less process margin. In the past, the systematic defects have been inspected by human-eyes. However the judgment by human-eyes is sometime unstable and not accurate. Moreover an enormous amount of time and labor will have to be expended on the one-by-one judgment for several thousands of hot-spot defects. In order to overcome these difficulties and improve the yield and manufacturability, the automated system, which can quantify the shape difference with high accuracy and speed, is needed. Inspection points could be increased for getting higher yield, if the automated system achieves our goal. Defect Window Analysis (DWA) system by using high-precision-contour extraction from SEM image on real silicon and quantifying method which can calculate the difference between defect pattern and non-defect pattern automatically, which was developed by Hitachi High-Technologies, has been applied to the defect judgment instead of the judgment by human-eyes. The DWA result which describes process behavior might be feedback to design or OPC or mask. This new methodology and evaluation results will be presented in detail in this paper.

Overlay control is becoming increasingly more important with the scaling of technology. It has become even more critical and more challenging with the move toward multiple-patterning lithography, where overlay translates into CD variability. Design rules and overlay have strong interaction and can have a considerable impact on the design area, yield, and performance. This paper offers a framework to study this interaction and evaluate the overall design impact of rules, overlay characteristics, and overlay control options. The framework can also be used for designing informed, design-aware overlay metrology and control strategies. In this work, The framework was used to explore the design impact of LELE doublepatterning rules and poly-line end extension rule defined between poly and active layer for different overlay characteristics (i.e., within-field vs. field-to-field overlay) and different overlay models at the 14nm node. Interesting conclusions can be drawn from our results. For example, one result shows that increasing the minimum mask-overlap length by 1nm would allow the use of a third-order wafer/sixth-order field-level overlay model instead of a sixth-order wafer/sixth-order field-level model with negligible impact on design.

Metrology measurement and defect inspection steps in routes are more pervasive than many people realize and the number continues to grow. Digging deeper, it turns out that E-beam metrology and defect inspection tools typically occupy the most overall steps and therefore are extremely critical tools for semiconductor development and manufacturing. The Critical Dimension Scanning Electron Microscope (CDSEM) is an E-beam tool responsible for image-based structural metrology measurements while the E-beam review (EBR) and E-beam inspection (EBI) tools are responsible for defect inspection. The CDSEM faces significant future challenges in a world where device architectures are changing (as with the FinFET device), increasing the need for more structural measurement parameters such as sidewall angle, height and undercut, than the CDSEM can deliver. These applications are now migrating to scattering-based tools, also referred to as model- or computational-based structural metrology techniques. We explore the history of the CDSEM, the key fundamental limits (primarily resolution) of the CDSEM preventing it from capturing these applications and assess if an image-based structural metrology tool is still needed given the niche that scattering tools are filling. The answer is yes. Next we discuss whether the CDSEM will eventually meet those needs or if other alternative solutions are needed. Lastly, we discuss an industry survey on which image-based technique holds the most promise to solve these challenges. Regarding defect inspection, resolution is also a concern for the applications that need to detect extremely small defects which current optical-based Brightfield tools cannot address. While resolution is a primary concern in structural metrology, current EBI and EBR tools possess the resolution needed for defect inspection and have extendibility through at least the next advanced technology node. We also explore the niche E-beam is filling in defect inspection, evaluate the idea that a better synergistic solution exists today between the CDSEM and the EBI tools and propose a future E-beam landscape where E-beam tool variety in future fabs is significantly reduced to enhance productivity.

To measure the new SEMATECH 9 nm node Intentional Defect Array (IDA) and subsequent small, complex defects, a methodology has been used to exploit the rich information content generated when simulating or acquiring several images of sub-wavelength-sized defects through best focus. These images, which are xy planes, collected using polarized illumination are stacked according to focus position, z, and through interpolation, volumetric pixels (“voxels”) are formed sized approximately 40 nm per side. From the image data, an intensity can be assigned to each (x,y,z) position. These four-dimensional matrices are extensively filtered for defect detection using multi-dimensional intensity thresholding, nearest-neighbor criteria, continuity requirements, and other techniques standard to optical defect inspection. A simulation example with oblique angles of illumination is presented. Experimental results are shown from the NIST λ=193 nm Microscope using full-field illumination. Volumetric data analysis is compared against the processing of single 2-D images. Defect metrics for comparing planar and volumetric data are developed with the potential shown for a five-fold increase in defect sensitivity using volumetric data versus conventional imaging.

In this paper we present a novel mode of electron beam inspection (EBI), entitled super wide optics (SWO) mode, which can effectively detect buried defects in tungsten (W) plugs and copper (Cu) wires. These defects are defects of interest (DOI) to integrated circuit (IC) manufacturers because they are not detectable in optical inspection, voltage contrast (VC) mode EBI or physical mode EBI. We used engineering systems to study two samples, a tungsten chemical mechanical polish (CMP) wafer and a copper CMP wafer with a silicon carbon nitride (SiCN) cap layer. EBI with our novel SWO mode was found to capture many dark defects on these two wafers. Furthermore, defect review with all three EBI modes found some of these dark defects were unique to SWO mode. For verification, physical failure analysis was performed on some SWO-unique DOI. The cross-sectional scanning electron microscope (SEM) images and transmission electron microscope (TEM) images confirmed that the unique DOI were buried voids in W-plugs and copper wire thinning caused by either buried particles or buried particle induced metal trench under-etch. These DOI can significantly increase the resistance of metal interconnects of IC chip and affect the chip yield. This new EBI mode can provide an in-line monitoring solution for these DOI, which does not exist before this study.

We applied epi-illumination diffraction phase microscopy to measure the amplitude and phase of the scattered field from a SEMATECH 22 nm node intentional defect array (IDA) wafer. We used several imaging processing techniques to remove the wafer’s underlying structure and reduce both the spatial and temporal noise and eliminate the system calibration error to produce stretched panoramic amplitude and phase images. From the stretched images, we detected defects down to 20 nm × 160 nm for a parallel bridge, 20 nm × 100 nm for perpendicular bridge, and 35 nm × 70 nm for an isolated dot.

Coherent diffractive imaging (CDI) using EUV/X-rays has proven to be a powerful microscopy method for imaging nanoscale objects. In traditional CDI, the oversampling condition limits its applicability to small, isolated objects. A new technique called keyhole CDI was demonstrated on a synchrotron X-ray source to circumvent this limitation. Here we demonstrate the first keyhole CDI result with a tabletop extreme ultraviolet (EUV) source. The EUV source is based on high harmonic generation (HHG), and our modified form of keyhole CDI uses a highly reflective curved EUV mirror instead of a lossy Fresnel zone plate, offering a ~10x increase in photon throughput of the imaging system, and a more uniform illumination on the sample. In addition, we have demonstrated a record 22 nm resolution using our tabletop CDI setup, and also the successful extension to reflection mode for a periodic sample. Combining these results with keyhole CDI will open the path to the realization of a compact EUV microscope for imaging general non-isolated and non-periodic samples, in both transmission and reflection mode.

Although fin metrology presents many challenges, the single crystal nature of the fins also provides opportunities to use a combination of measurement methods to determine stress and pitch. While the diffraction of light during a scatterometry measurement is well known, X-ray diffraction from a field (array) of single crystal silicon fins can also provide important information. Since some fins have Si_1-xGe_x alloys at the top of the fin, determination of the presence of stress relaxation is another critical aspect of fin characterization. Theoretical studies predict that the bi-axially stressed crystal structure of pseudomorphic alloy films will be altered by the fin structure. For example, one expects it will be different along the length of the fin vs the width. Reciprocal space map (RSM) characterization can provide a window in the stress state of fins as well as measure pitch walking and other structural information. In this paper, we describe the fundamentals of how RSMs can be used to characterize the pitch of an array of fins as well as the stress state. We describe how this impacts the optical properties used in scatterometry measurement.

Photoresist shrinkage (i.e., line slimming) is an important systematic uncertainty source in critical dimension-scanning electron microscope (CD-SEM) metrology of lithographic features [1] [2] [3] [4] [5]. It influences both the precision and the accuracy of CD-SEM measurements, while locally damaging the sample. Minimization or elimination of shrinkage is desirable, yet elusive. This error source will be a factor in CD-SEM metrology on polymer materials in EUV lithography. Recent work has demonstrated improved understanding of the trends in the shrinkage response depending on electron beam and target parameters in static measurements [2] [3] [4] [5] [6]. Some research has highlighted a second mode of shrinkage that is apparent over time and progresses as a function of time between consecutive measurements, a form of “dynamic shrinkage” that appears to be activated by electron beam, in which the activated feature perpetually and logarithmically shrinks [7] [8]. Another work has demonstrated that as pitches continue to get smaller with resulting reductions in spaces between lines, charging may emerge as an additional, competing, unpredictable error source for CD-SEM metrology on dense photoresist features, an issue that is predicted to become more common as these spaces become more confined [9]. In this work, we explore the static shrinkage behaviors of various EUV photoresists into the 16 nm half-pitch node, with samples generated using the advanced EUV lithography capable of generating such tight pitches [10]. Dynamic shrinkage behavior was explored on these materials last year [15]. The static shrinkage behaviors will be validated to show compliance with the SEMATECH shrinkage model [5] [6] on small EUV resist features. Using the results of the model fits, a simulation study will predict the shrinkage trends at future nodes. Further studies will confirm whether or not charging phenomena are observable, and the beginning of a charging simulation study will be discussed.

The mechanism of photoresist shrinkage induced by electron-beam (EB) irradiation was studied. A precise cross-sectional profile of a photoresist pattern was obtained by a scanning transmission electron microscope (STEM) after atomic layer deposition of HfO₂ on the sample patterns. Photoresist lines and spaces fabricated with positive-tone development and negative-tone development were exposed to an EB with much higher dose than a practical dose (to accelerate shrinkage intentionally). The obtained STEM images of the patterns before and after EB irradiation show that the shrinkage of the negative-tone-developed patterns is smaller than that of the positive-tone-developed patterns. This observation is explained by the fact that negative-tone-developed photoresist molecules do not contain protection groups, whose volatilization caused by EB irradiation is one of the origins of shrinkage. Another finding is that the EB irradiation causes top-rounding and necking of the pattern profile as well as linewidth slimming. The rounding of the pattern top profile suggests that the pattern’s shape was elastically deformed. In addition, EB irradiation only onto the spaces caused sidewall shrinkage and a necking profile, although no electrons were irradiated directly onto the pattern. These phenomena are considered to be due to the electrons scattered from the spaces to the pattern sidewall. Finally, a Monte Carlo simulation of electron scattering showed that the distribution of the deposited EB energy on the pattern surface corresponds to the above-described change in pattern shape. Consequently, these observations and simulation results clarify the importance of the effect of elastic shape change and the impact of the electrons scattered from the underlying layer onto the sidewall in the mechanism of photoresist shrinkage.

We have demonstrated that transmission critical dimension small angle X-ray scattering (CD-SAXS) provides high accuracy and precision CD measurements on advanced 3D microelectronic architectures. The competitive advantage of CD-SAXS over current 3D metrology methods such as optical scatterometry is that CD-SAXS is able to decouple and fit cross-section parameters without any significant parameter cross-correlations. As the industry aggressively scales beyond the 22 nm node, CD-SAXS can be used to quantitatively measure nanoscale deviations in the average crosssections of FinFETs and high-aspect ratio (HAR) memory devices. Fitting the average cross-section of 18:1 isolated HAR contact holes with an effective trapezoid model yielded an average pitch of 796.9 ± 0.4 nm, top diameter of 70.3 ± 0.9 nm, height of 1088 ± 4 nm, and sidewall angle below 0.1°. Simulations of dense 40:1 HAR contact holes and FinFET fin-gate crossbar structures have been analyzed using CD-SAXS to inquire the theoretical precision of the technique to measure important process parameters such as fin CD, height, and sidewall angle; BOX etch recess, thickness of hafnium oxide and titanium nitride layers; gate CD, height, and sidewall angle; and hafnium oxide and titanium nitride etch recess. The simulations of HAR and FinFET structures mimic the characteristics of experimental data collected at a synchrotron x-ray source. Using the CD-SAXS simulator, we estimate the measurement capabilities for smaller similar structures expected at future nodes to predict the applicability of this technique to fulfill important CD metrology needs.

The uses of strained channel became prevalent at the 65 nm node and have continued to be a large part of logic device performance improvements in every technology generation. These material and integration innovations will continue to be important in sub-22nm devices, and are already being applied in finFET devices where total available in-channel strains are potentially higher. The measurement of structures containing these materials is complicated by the intrinsic correlation of the measured optical thickness and variation of optical properties with strain, as well as the dramatic reduction in total volume of the device. Optical scatterometry has enabled characterization of the feature shape and dimensions of complex 3D structures, including non-planar transistors and memory structures. Ellipsometric methods have been successfully applied to the measurement of thin films of SiGe and related strained structures. A direction for research is validating that the thin film stress results can be extended into the much more physically complex 3D shape. There are clear challenges in this: the stress in a SiGe fin is constrained to match the underlying Si along one axis, but the sides and top are free, leading to very large strain gradients both along the fin width and height. Practical utilization of optical techniques as a development tool is often limited by the complexity of the scatterometry model and setup, and this added material complexity presents a new challenge. In this study, generalized spectroscopic ellipsometric measurements of strained grating was undertaken, in parallel with reference cross sectional and top down SEM data. The measurements were modeled for both anisotropy calculations, as well as full scatterometry calculations, fitting the strain and structure. The degree to which strain and CD can be quickly quantified in an optical model is discussed. Sum decomposition method has been implemented to extract the effective anisotropic coefficients and a discussion on the effect of anisotropy toward modeling is presented. Finally, errors in the scatterometry measurement are analyzed, and the relative strengths and limitations of these optical measurements compared.

Photoacoustic nanometrology using coherent extreme ultraviolet (EUV) light detection is a unique and powerful tool for probing ultrathin films with a wide range of mechanical properties and thicknesses well under 100 nm. In this technique, short wavelength acoustic waves are generated through laser excitation of a nano-patterned metallic grating, and then probed by diffracting coherent EUV beams from the dynamic surface deformation. Both longitudinal and surface acoustic waves within thin films and metallic nanostructures can be observed using EUV light as a phase-sensitive probe. The use of nanostructured metal transducers enables the generation of particularly short wavelength surface acoustic waves, which truly confine the measurement within the ultrathin film layer of interest, to thicknesses < 50 nm for the first time. Simultaneous measurement of longitudinal and transverse surface wave velocities yields both the Young’s modulus and Poisson’s ratio of the film. In the future, this approach will make possible precise mechanical characterization of nanostructured systems at sub-10 nm length scales.

One of the key challenges to high resolution resist patterning is pattern collapse. Using a new scanning probe microscopy (SPM), Peak Force^TM tapping, we map nano-mechanical properties-- modulus, adhesion, and dissipation-- of the exposed/developed resist structures with sub-10 nm resolution. Properties are compared across a carbon based negative resist with and without cross-linking. The SPM technique reveals that cross-linking significantly enhances the mechanical properties to give a champion resolution of sub 20 nm half-pitch in a chemically amplified negative resist system. Beyond mechanical properties, surface morphology and redistribution kinetics were examined using complementary techniques and reveal additional benefits with cross-linking.

In this paper we will review typical applications of photoluminescence (PL) metrology in high volume LED manufacturing environments. PL is a well-established method for analysis of semiconductor properties. The technique is non-contact, non-destructive and rapid. We will describe the principles of the measurement and review PL data from LED process wafers. We will discuss how PL measurement results like peak wavelength, dominant wavelength and PL intensity are obtained. We will summarize the accuracy, precision, stability and other considerations of the measurement. Finally, metrology considerations for manufacturing LEDs on large diameter substrates, including the possibility of 8” silicon substrates, will be presented.

In this paper, we present a comparison of profile measurements of vertical field effect transistor (FinFET) fin arrays by optical critical dimension (OCD) metrology and critical dimension small angle X-ray scattering (CD-SAXS) metrology. Spectroscopic Muller matrix elements measurements were performed at various azimuthal angles for OCD, and X-ray diffraction intensities were collected for different incident angles in CD-SAXS measurements. A common trapezoidal model was used to compute the OCD and CD-SAXS signatures, using rigorous coupled wave (RCW) analysis and a 2D Fourier transform, respectively. Profile parameters, some material parameters, and instruments parameters were adjusted by a non-linear fitting procedure of the data. Results from both measurement techniques were compared and found in reasonable agreement with one another, although some of the parameters have differences that exceed the estimated uncertainties.

Gate patterning control for 28nm Fully Depleted Silicon On Insulator (FD-SOI) technology faces several challenges. For lithography and etch , usage of DoseMapper requires extensive and accurate metrology to compute adequate dose recipes. From etch side we will have to control both polysilicon and metal gate CD’s. For device integration it will be extremely important to monitor N and PMOS devices and get appropriate gate profiles since transistor morphology is a key contributor to device performances. In parallel of CD control, thin silicon film on top of buried oxide layer will also require a strict control of its thickness. Scatterometry is the only way to get all these informations from a patterned environment [1]. We will show in this paper how scatterometry has been proven to be accurate enough to support the realization of DOE’s for metal gate profile optimisation at gate patterning without doing hundred’s of TEM. Scatterometry results are correlated to parametric tests and TEM for ultimate validation.

Optical critical dimension (OCD) metrology using scatterometry has been demonstrated to be a viable solution for fast and non-destructive in-line process control and monitoring. As extreme ultraviolet lithography (EUVL) is more widely adopted to fabricate smaller and smaller patterns for electronic devices, scatterometry faces new challenges due to several reasons. For 14nm node and beyond, the feature size is nearly an order of magnitude smaller than the shortest wavelength used in scatterometry. In addition, thinner resist layer is used in EUVL compared with conventional lithography, which leads to reduced measurement sensitivity. Despite these difficulties, tolerance has reduced for smaller feature size. In this work we evaluate 3D capability of scatterometry for EUV process using spectroscopic ellipsometry (SE). Three types of structures, contact holes, tip-to-tip, and tip-to-edge, are studied to test CD and end-gap metrology capabilities. The wafer is processed with focus and exposure matrix. Good correlations to CD-SEM results are achieved and good dynamic precision is obtained for all the key parameters. In addition, the fit to process provides an independent method to evaluate data quality from different metrology tools such as OCD and CDSEM. We demonstrate 3D capabilities of scatterometry OCD metrology for EUVL using spectroscopic ellipsometry, which provides valuable in-line metrology for CD and end-gap control in electronic circuit fabrications.

CD and shape control of extreme ultraviolet lithography (EUVL) structures is critical to ensure patterning performance at the 10 nm technology node and beyond. The optimum focus/dose control by EUV scanner is critical for CD uniformity, and the scanner depends on reliable and rapid metrology feedback to maintain control. The latest advances in scatterometry such as ellipsometry (SE), reflectometry (NISR), and Mueller matrix (MM) offers complete pattern profile, critical dimensions (CD), side-wall angles, and dimensional characterization. In this study, we will present the evaluation results of CD uniformity and focus dose sensitivity of line and space EUV structures at the limit of current ASML NXE 3100 scanner printability and complex 3D EUV structures. The results will include static and dynamic precision and CD-SEM correlation data.

Fast and robust metrologies for retrieving large amount of accurate wafer data is the key to meet the ever stricter semiconductor manufacturing process control such as critical dimension (CD) and overlay as the industry moving towards 22 nm or smaller designs. Scatterometry emerges due to its non-destructivity and rapid availability for accurate wafer data. In this paper we simulate the ability of a new scatterometry method to show its accurate control over lithography model and OPC model calibrations. The new method directly utilizes scattering signals of scatterometry to control the process instead of using numerically analyzed dimensional parameters such as CD and side wall angle (SWA). The control can be achieved by optimizing the scattering signal of one process by tuning numerical aperture (NA), sigma, or lens aberration to match the signal of the target process. In this work only sigma is used for optimization. We found that when the signals of both processes are matched with minimized optimization error, CD of the grating profiles on the wafers are also minimized. This result enables valid lithography process control and model calibration with the new method.

The ongoing transition from 2D to 3D structures in logic and memory has led to an increased adoption of scatterometry CD (SCD) for inline metrology. However, shrinking device dimensions in logic and high aspect ratios in memory represent primary challenges for SCD and require a significant breakthrough in improving signal-to-noise performance. We present a report on the new generation of SCD technology, enabled by a new laser-driven plasma source. The developed light source provides several key advantages over conventional arc lamps typically used in SCD applications. The plasma color temperature of the laser driven source is considerably higher than available with arc lamps resulting in >5X increase in radiance in the visible and >10X increase in radiance in the DUV when compared to sources on previous generation SCD tools while maintaining or improving source intensity noise. This high radiance across such a broad spectrum allows for the use of a single light source from 190-1700nm. When combined with other optical design changes, the higher source radiance enables reduction of measurement box size of our spectroscopic ellipsometer from 45×45um box to 25×25um box without compromising signal to noise ratio. The benefits for 1×nm SCD metrology of the additional photons across the DUV to IR spectrum have been found to be greater than the increase in source signal to noise ratio would suggest. Better light penetration in Si and poly-Si has resulted in improved sensitivity and correlation breaking for critical parameters in 1xnm FinFET and HAR flash memory structures.

Resist spin coating has already been applied to IC industry for a very long time. Uniform spin coat of photoresist has been demonstrated on 12” wafers with conventional 6” and 8” methods. Meanwhile, resist dispense volume reduction has also been widely studied and investigated. In our paper, we focus on the physical properties of photoresist and prewet solvent. We try to figure out the interfacial behavior/mechanism between ArF resist and its related pre-wet solvent by systematic methods and DOE splits. In the experiments, different ArF resists among various solvent systems and two distinct pre-wet systems are tested and researched. Certain ArF resists generate smaller dispense volume compared with other PRs even under the same process condition. Eventually, from the splits we find out the trend which correlates to the interaction between resist and pre-wet solvent. The trend proves that our hypothesis is correct. The conclusion will contribute to our future resist selection. The conclusion will also provide new resist design concept to resist vendors. Basic studies and experiments are carried out under our limited resources, equipment and time. We have tried our best to find out the mechanism and have proved it.

As device features continue to shrink, achieving acceptable yields becomes increasingly challenging. In the photolithography process, mask error is one of the most critical error sources, since any imperfections on a mask will be amplified and transferred onto a wafer due to Mask Error Enhancement Factor (MEEF) [1]. Furthermore, due to complexity of lithography optical proximity effect correction in advanced technology nodes, more and more 2D structures are applied into mask patterns. Furthermore, more 2D pattern configurations are susceptible to pattering failures due to their much high MEEF factor than 1D pattern. As a result, the conventional mask error control mechanisms for 1D [2] [3] [4] only, such as mean-to-target (MTT) and CD uniformity, are no longer adequate to deal with high MEEF 2D structures. In this paper, a novel 2D structure mask error monitoring technique is introduced to prevent fatal wafer printing errors such as CD error, line-end pull back and other pattern distortions to ensure high quality mask manufacturing and to improve wafer yield in advanced technology nodes. We will demonstrate the flow using typical 2D structure test patterns in 28nm technology node design or beyond. The SEM image would be taken and measured by this novel technique are used to monitor mask fidelity performance. This monitoring technique is based on Image-to-layout, as one of Anchor Semiconductor’s pattern centric techniques, which can extract contour and convert it into pattern layouts from SEM or optical image of masks. Further pattern signature analysis can be performed on the pattern (inner /outer vertex, space distance and edge distance), so that we can quickly identify target locations for 2D pattern measurements. We monitor the severity of 2D corner rounding on selected 28nm design rule masks by Pattern Fidelity (PF) ratio and correlate them with wafer printing results. 2D pattern measurement techniques and PF ratio monitoring system from SEM image is an effective approach to ensure high quality mask making in 28nm and advanced technology nodes. This PF ratio monitoring from 2D pattern SEM images is an effective approach to ensure high quality mask making in advanced 28nm node and beyond, which can overcome the inadequacy of current 1D measurement only method, especially for the masks are generated without source mask optimization (SMO) [6].

Advanced thermal annealing processes used for transistor enhancing for the state of the art process nodes induce wafer grid deformations. RTA (Rapid Thermal Anneal) and LSA (Laser Scanning Anneal) processes are a few examples. High Order Wafer Alignment (HOWA) method is an effective wafer alignment strategy for wafers with distorted grid signature especially when wafer-to-wafer grid distortion variations are also present. However, usage of HOWA in high volume production environment requires 1) careful initial determination of optimum polynomial order and alignment sampling to be implemented, and 2) matched tool monitoring and controlling strategies and infrastructures to avoid potential HOWA induced drawbacks (i.e. alignment walking).

As device dimensions shrink, the measurement of layer-to-layer overlay is becoming increasingly important. Overlay is currently measured using target patterns fabricated within scribe lines. However, there are residual errors between the measurement values at the scribe lines and the actual values at the circuit pattern regions. Therefore, in-die overlay measurements using circuit patterns are required for precise overlay control. We have developed an in-die overlay measurement method based on SEM images. The overlay is directly measured by comparing a golden image and a test image captured at the circuit pattern region. Each layer is automatically recognized from the images, and the placement error between the two images is determined and used to calculate the overlay. This enables measurement without a specially designed target pattern or the setting up of measurement cursors. In the simulation experiments, the proposed method has linearity and sensitivity for the sub-pixel-order overlay even if the patterns have size variations. The basic performance of this method was evaluated using a defect review SEM. For advanced memory devices, a measurement repeatability of less than 1.0 nm was achieved, and a reasonable wafer map of the overlay was obtained.

Defect inspection of EUV substrates and mask blanks must be controlled consistently to ensure repeatable and accurate defect counts. Initial sensitivity must be maintained without producing false counts. Various constructed and native defect monitors are created on substrates to track inspection tool performance. Remedies are applied to an inspection tool when monitors go out of control.

Traditionally, an optical proximity correction model is to evaluate the resist image at a specific depth within the photoresist and then extract the resist contours from the image. Calibration is generally implemented by comparing resist contours with the critical dimensions (CD). The wafer CD is usually collected by a scanning electron microscope (SEM), which evaluates the CD based on some criterion that is a function of gray level, differential signal, threshold or other parameters set by the SEM. However, the criterion does not reveal which depth the CD is obtained at. This depth inconsistency between modeling and SEM makes the model calibration difficult for low k₁ images. In this paper, the vertical resist profile is obtained by modifying the model from planar (2D) to quasi-3D approach and comparing the CD from this new model with SEM CD. For this quasi-3D model, the photoresist diffusion along the depth of the resist is considered and the 3D photoresist contours are evaluated. The performance of this new model is studied and is better than the 2D model.

Fingerprint edge roughness (FER) is proposed to characterize high frequency roughness of fingerprint pattern edges assembled by lamella forming block copolymer (BCP). The FER is a roughness index which does not include the roughness component of the fingerprint curvature. A technique to evaluate FER by using CD-SEM is also proposed. Centerline of the fingerprint patterns were extracted by utilizing binarization and slimming algorithm, and line width, line width roughness and line edge roughness along the centerline were measured. The FER thus measured showed a good agreement with those determined by utilizing conventional line edge roughness analyzing algorithm. The FERs of fingerprint patterns assembled with various BCP formulations were analyzed. As a result, the proposed technique successfully detected the line edge roughness difference between each BCP formulations with different compositions. The results indicate that the FER might be a useful index to evaluate the patterning performance of BCP as a material for DSA process. The proposed technique will provide a method for fast and easy development of BCP materials and processes

In dark-field particle inspection, the limiting factor for sensitivity is the amount of background scatter due to substrate roughness. This scatter forms a speckle pattern and shows an intensity distribution with a long tail. To reduce falsepositives to an acceptable level, a high detection threshold should be chosen such that the tail of the background distribution is avoided. We have modeled an optimized illumination mode, that reduces the variance in the background distribution. This illumination mode illuminates the substrate from multiple azimuth angles. We show that the speckle patterns generated by each azimuth angle can be independent from each other. Therefore by combining the angles, the variance of the background signal is reduced. We show that for the parameters of our inspection system the detection threshold can be reduced by a factor three, resulting in a lower detection limit that is 20% smaller in particle size. The change in the background scattering distribution was confirmed by experiments.

We introduced a very simple overlay feed forward correction based on lot data issued from previous lithography operations. Simple method for correction factor optimization was also proposed. We applied this method in various cases based on 28nm node early production: implants lithography on 248nm tools, contact holes double patterning on 193nm immersion tool, and we also tried to improve contact holes patterning based on 248nm lithography data. All analysis were based on early production 28nm node data mixing 28LP and 28FDSOI technologies. We first optimized the correction based on our simple approach, and then compute the dispersion of all linear overlay parameters. Maximum modeled overlay error was also computed. In most cases we obtained significant improvements. The interest of such a very simple approach that requires reduced software development and allows simple implementation was thus demonstrated.

We introduced a simple method based on scatterometry measurement performed on dense contact holes matrix to investigate intrafield focus deviation on 28nm FDSOI real production wafers at contact holes patterning lithography operation. A complex three-dimensional scatterometry model with all patterned resist geometrical parameters left as degree of freedom. Then simple linear relationships between patterned resist geometrical parameters on the one hand, and applied dose and focus offset on the other hand were used to determine a focus and dose decorrelation model. This model was then used to investigate the effect of ASML AGILE^TM scanner option on intrafield focus deviation. A significant 16% intrafield focus standard deviation improvement was found with AGILE^TM, which validated our method and shows the possibilities of AGILE^TM option for intrafield focus control. This focus investigation method may be used to improve advanced CMOS manufacturing process control.

A method for automatic computation of parameter derivatives of numerically computed light scattering signals is demonstrated. The finite-element based method is validated in a numerical convergence study, and it is applied to investigate the sensitivity of a scatterometric setup with respect to geometrical parameters of the scattering target. The method can significantly improve numerical performance of design optimization, parameter reconstruction, sensitivity analysis, and other applications.

This paper discusses the defect density detection and analysis methodology using advanced optical wafer inspection capability to enable accelerated development of a DSA process/process tools and the required inspection capability to monitor such a process. The defectivity inspection methodologies are optimized for grapho epitaxy directed self-assembly (DSA) contact holes with 25 nm sizes. A defect test reticle with programmed defects on guide patterns is designed for improved optimization of defectivity monitoring. Using this reticle, resist guide holes with a variety of sizes and shapes are patterned using an ArF immersion scanner. The negative tone development (NTD) type thermally stable resist guide is used for DSA of a polystyrene-b-poly(methyl methacrylate) (PS-b-PMMA) block copolymer (BCP). Using a variety of defects intentionally made by changing guide pattern sizes, the detection rates of each specific defectivity type has been analyzed. It is found in this work that to maximize sensitivity, a two pass scan with bright field (BF) and dark field (DF) modes provides the best overall defect type coverage and sensitivity. The performance of the two pass scan with BF and DF modes is also revealed by defect analysis for baseline defectivity on a wafer processed with nominal process conditions.

In this paper, we show the 2D and 3D scatterometry simulation software which has spectroscopy calculation and optimization algorithm systems. The scatterometry analysis for 3D-structure requires a lot of memory and along calculation time. The calculation is sped up by parallel computing using the GPU (Graphics Processor Unit). Here, we use the programming language CUDA (Compute Unified Device Architecture) and CULA (CULApack) for the NVIDIA GPU. Then, we use the real-coded GA (RCGA) to increase the population, to make a more sensitive solution and to get better fitting groove figures. The scatterometry characteristic is examined by choosing the n-th power cosine type period groove.

High-K/metal gate technology, introduced by Intel, to replace the conventional oxide gate dielectric and polysilicon gate has truly revolutionized transistor technology more than any other change over the last 40 years. First introduced at the 45nm node, this complex process has now been adopted for advanced nodes. The capability of picosecond ultrasonic measurements (PULSE^TM) for in-line monitoring of High-K/metal gate structures was evaluated and the benefits of this technology for measuring various structures including SRAM, pad array, and line array key with excellent correlation to cross sectional TEM was demonstrated. We have shown that, only a direct measurement of SRAM structures can represent true variations of the metal gate height due to CMP process and is strongly affected by the design and layout of pattern, including pattern density, dummy design, and spacing. The small spot, non-contact, non-destructive nature of this technology allows for in-line measurements directly on these structures with excellent repeatability at a very high throughput.

In this paper, we propose advanced overlay stability control improving conventional stability control, Baseliner™ and reference wafers with new vertical structure for effective stability control. We verify improved overlay stability control experimentally by using this stability control method. Also we suggest that additional improvements can be achieved by controllable process terms. For focus stability control, we make reference wafers which can measure overlay and focus simultaneously on the same wafer to minimize monitoring wafers.

This paper presents a methodology for detecting defects more effectively that have a substantial yield impact on several critical layers using a simulation program, which is considerably helpful in analyzing defects on the wafer. First, this paper presents a simple analysis method that uses mathematical treatment for multi thin film layers. This instantly gives us a highly intuitive idea for selecting an inspection mode based on the reflectivity and transmittivity. Second, we introduce numerical method for wafer defect of interest with finite difference time domain (FDTD) method, and provide correlation between the expectation and experimental results. The goal of these studies is to determine the feasibility of implementing theoretical approaches with numerical method at wafer defect inspection. Overall, this paper discusses the effective wafer inspection methodology and the advantages of defect simulation with numerical analysis at semiconductor manufacturing for accelerated development of advanced design node devices.

Continued tightening of overlay control budget in semiconductor lithography drives the need for improved metrology capabilities. Aggressive improvements are needed for overlay metrology speed, accuracy and precision. This paper is dealing with the on product metrology results of a scatterometry based platform showing excellent production results on resolution, precision, and tool matching for overlay. We will demonstrate point to point matching between tool generations as well as between target sizes and types. Nowadays, for the advanced process nodes a lot of information is needed (Higher order process correction, Reticle fingerprint, wafer edge effects) to quantify process overlay. For that purpose various overlay sampling schemes are evaluated: ultra- dense, dense and production type. We will show DBO results from multiple target type and shape for on product overlay control for current and future node down to at least 14 nm node. As overlay requirements drive metrology needs, we will evaluate if the new metrology platform meets the overlay requirements.

In order to fulfill the ever tightening requirements of advanced node overlay budgets, overlay metrology is becoming more and more sensitive to even the smallest imperfections in the metrology target. Under certain circumstances, inaccuracy due to such target imperfections can become the dominant contribution to the metrology uncertainty and cannot be quantified by the standard TMU contributors. In this paper we describe a calibration method that makes the overlay measurement robust to target imperfections without diminishing its sensitivity to the target overlay. The basic assumption of the method is that overlay measurement result can be approximated as the sum of two terms: the accurate overlay and the measurement inaccuracy (independently of the conventional contributors). While the first term (the “real overlay”) is robust it is known that the overlay target inaccuracy depends on the measurement conditions. This dependence on measurement conditions is used to estimate quantitative inaccuracy by means of the overlay quality merit which was described in previous publications. This paper includes the theoretical basis of the method as well as experimental validation.

With decreasing of critical dimension (CD), the availability of depth of focus (DOF) goes down from technology node to technology node. Monitoring and controling of scanner focus on product wafers will be necessary. A technique entitled Iso-Dense Focus Monitor(IDFM) is developed to measure the focus errors of scanner systems. This IDFM method uses double side chrome mask and iso-dense binary overlay mark. The accuracy of this IDFM technique using binary mark may equal to the conventional PGFM method, and the IDFM technique only expose the wafer one time comparing with Z-SPIN which may expose two times. This method was simulated and also implemented on a litho tool of SMEE SSA600/10.

Atomic force microscopy (AFM) is increasingly used in the semiconductor industry as a versatile monitoring tool for highly critical lithography and etching process steps. Applications range from the inspection of the surface roughness of new materials, over accurate depth measurements to the determination of critical dimension structures. The aim to address the rapidly growing demands on measurement uncertainty and throughput more and more shifts the focus of attention to the AFM tip, which represents the crucial link between AFM tool and the sample to be monitored. Consequently, in order to reach the AFM tool’s full potential, the performance of the AFM tip has to be considered as a determining parameter. Currently available AFM tips made from silicon are generally limited by their diameter, radius, and sharpness, considerably restricting the AFM measurement capabilities on sub-30nm spaces. In addition to that, there’s lack of adequate characterization structures to accurately characterize sub-25nm tip diameters. Here, we present and discuss a recently introduced AFM tip design (T-shape like design) with precise tip diameters down to 15nm and tip radii down to 5nm fabricated from amorphous, high density diamond-like carbon (HDC/DLC) using electron beam induced processing (EBIP). In addition to that advanced design, we propose a new characterizer structure, which allows for accurate characterization and design control of sub-25nm tip diameters and sub-10nm tip edges radii. We demonstrate the potential advantages of combining a small tip shape design, i.e. tip diameter and tip edge radius, and an advanced tip characterizer for the semiconductor industry by the measurement of advanced lithography patterns.

The semiconductor industry is moving toward 20nm nodes and below. As the Overlay (OVL) budget is getting tighter at these advanced nodes, the importance in the accuracy in each nanometer of OVL error is critical. When process owners select OVL targets and methods for their process, they must do it wisely; otherwise the reported OVL could be inaccurate, resulting in yield loss. The same problem can occur when the target sampling map is chosen incorrectly, consisting of asymmetric targets that will cause biased correctable terms and a corrupted wafer. Total measurement uncertainty (TMU) is the main parameter that process owners use when choosing an OVL target per layer. Going towards the 20nm nodes and below, TMU will not be enough for accurate OVL control. KLA-Tencor has introduced a quality score named ‘Qmerit’ for its imaging based OVL (IBO) targets, which is obtained on the-fly for each OVL measurement point in X & Y. This Qmerit score will enable the process owners to select compatible targets which provide accurate OVL values for their process and thereby improve their yield. Together with K-T Analyzer’s ability to detect the symmetric targets across the wafer and within the field, the Archer tools will continue to provide an independent, reliable measurement of OVL error into the next advanced nodes, enabling fabs to manufacture devices that meet their tight OVL error budgets.

The new measuring method that we developed executes a contour shape analysis that is based on the pattern edge information from a SEM image. This analysis helps to create a highly precise quantification of every circuit pattern shape by comparing the contour extracted from the SEM image using a CD measurement algorithm and the ideal circuit pattern. The developed method, in the next phase, can generate four shape indices by using the analysis mass measurement data. When the shape index measured using the developed method is compared the CD, the difference of the shape index and the CD is negligibly small for the quantification of the circuit pattern shape. In addition, when the 2D patterns on a FEM wafer are measured using the developed method, the tendency for shape deformations is precisely caught by the four shape indices. This new method and the evaluation results will be presented in detail in this paper.