18 April 2013 High order wafer alignment for 20nm node logic process
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Abstract
Advanced thermal annealing processes used for transistor enhancing for the state of the art process nodes induce wafer grid deformations. RTA (Rapid Thermal Anneal) and LSA (Laser Scanning Anneal) processes are a few examples. High Order Wafer Alignment (HOWA) method is an effective wafer alignment strategy for wafers with distorted grid signature especially when wafer-to-wafer grid distortion variations are also present. However, usage of HOWA in high volume production environment requires 1) careful initial determination of optimum polynomial order and alignment sampling to be implemented, and 2) matched tool monitoring and controlling strategies and infrastructures to avoid potential HOWA induced drawbacks (i.e. alignment walking).
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Bumhwan Jeon, Bumhwan Jeon, Shyam Pal, Shyam Pal, Sohan Mehta, Sohan Mehta, Subramany Lokesh, Subramany Lokesh, Yun Tao Jiang, Yun Tao Jiang, Chen Li, Chen Li, Mark Yelverton, Mark Yelverton, Yayi Wei, Yayi Wei, } "High order wafer alignment for 20nm node logic process", Proc. SPIE 8681, Metrology, Inspection, and Process Control for Microlithography XXVII, 868110 (18 April 2013); doi: 10.1117/12.2010709; https://doi.org/10.1117/12.2010709
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