10 April 2013 In-die overlay metrology method using defect review SEM images
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Abstract
As device dimensions shrink, the measurement of layer-to-layer overlay is becoming increasingly important. Overlay is currently measured using target patterns fabricated within scribe lines. However, there are residual errors between the measurement values at the scribe lines and the actual values at the circuit pattern regions. Therefore, in-die overlay measurements using circuit patterns are required for precise overlay control. We have developed an in-die overlay measurement method based on SEM images. The overlay is directly measured by comparing a golden image and a test image captured at the circuit pattern region. Each layer is automatically recognized from the images, and the placement error between the two images is determined and used to calculate the overlay. This enables measurement without a specially designed target pattern or the setting up of measurement cursors. In the simulation experiments, the proposed method has linearity and sensitivity for the sub-pixel-order overlay even if the patterns have size variations. The basic performance of this method was evaluated using a defect review SEM. For advanced memory devices, a measurement repeatability of less than 1.0 nm was achieved, and a reasonable wafer map of the overlay was obtained.
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Jaehyoung Oh, Gwangmin Kwon, Daiyoung Mun, Hyungwon Yoo, Sungsu Kim, Tae hui Kim, Minoru Harada, Yohei Minekawa, Fumihiko Fukunaga, Mari Nozoe, "In-die overlay metrology method using defect review SEM images", Proc. SPIE 8681, Metrology, Inspection, and Process Control for Microlithography XXVII, 868111 (10 April 2013); doi: 10.1117/12.2010728; https://doi.org/10.1117/12.2010728
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