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18 April 2013 In-line high-K/metal gate monitoring using picosecond ultrasonics
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High-K/metal gate technology, introduced by Intel, to replace the conventional oxide gate dielectric and polysilicon gate has truly revolutionized transistor technology more than any other change over the last 40 years. First introduced at the 45nm node, this complex process has now been adopted for advanced nodes. The capability of picosecond ultrasonic measurements (PULSETM) for in-line monitoring of High-K/metal gate structures was evaluated and the benefits of this technology for measuring various structures including SRAM, pad array, and line array key with excellent correlation to cross sectional TEM was demonstrated. We have shown that, only a direct measurement of SRAM structures can represent true variations of the metal gate height due to CMP process and is strongly affected by the design and layout of pattern, including pattern density, dummy design, and spacing. The small spot, non-contact, non-destructive nature of this technology allows for in-line measurements directly on these structures with excellent repeatability at a very high throughput.
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C. W. Hsu, R. P. Huang, J. Chen, J. Tan, H. F. Huang, Welch Lin, Y. L. Hsieh, W. C. Tsao, C. H. Chen, Y. M. Lin, C. H. Lin, H. K. Hsu, K. Liu, C. C. Huang, J. Y. Wu, J. Dai, and P. Mukundhan "In-line high-K/metal gate monitoring using picosecond ultrasonics", Proc. SPIE 8681, Metrology, Inspection, and Process Control for Microlithography XXVII, 86811C (18 April 2013);

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