Circuit layout and design rules have continued to shrink to the point where a few nanometers of pattern misalignment can negatively impact process capability and device yields. As wafer processes and film stacks have become more complex, overlay and alignment performance in high-volume manufacturing (HVM) have become increasingly sensitive to process and tool variations experienced by incoming wafers. Current HVM relies on overlay control via advanced process control (APC) feedback, single-exposure tool grid stability, scanner-to-scanner matching, correction models, sampling strategies, overlay mark design, and metrology. However, even with improvements to those methods, a large fraction of the uncorrectable errors (i.e., residuals) still remains. While lower residuals typically lead to increased yield performance, it is difficult to achieve in HVM due to the large combinations of wafer history in terms of prior tools, recipes, and ongoing process conversions. Hence, it is critical to understand the effect of residual errors on measurement sampling and model parameters to enable process control. In this study, we investigate the following: residual errors of sub-40nm processes as a function of correction models, sensitivity of the model parameters to residue, and the impact of data quality.