As device design rule has been made pattern size shrink, overlay control has become one of the most critical issues for semiconductor manufacturing. Advanced lithographic exposure tools, such as EUV and i-ArF scanners, require high-order overlay corrections. In conventional overlay metrology, several overlay targets are arranged in scribe area on product wafer. However, the number of measurement point is not sufficient for high-order overlay corrections and these positions are too far from device patterns to estimate its overlay. High-order overlay corrections should be calculated from overlay measurement data by using a considerable number of in-die targets near device pattern. In this case, smaller target area size is expected for advanced lithography. In this paper we introduce in-die overlay metrology by using critical dimension scanning electron microscope (CD-SEM). It has several advantages over a conventional optical overlay measurement tool, 1) the target area size can be set smaller than 5 x 5 μm, 2) the size and feature of measurement pattern can be set similar to device design, therefore WIS (Wafer Induced Shift) is assumed to be small, 3) TIS (Tool Induced Shift) by CD-SEM, which we measure, is small. Furthermore, we show repeatability and accuracy of the overlay measurement by CD-SEM. And overlay distribution measured by die-to-die can be verified by sufficient number of the dedicated targets in-die.