29 March 2013 Sustainable scaling technique on double-patterning process
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The double patterning process has become a technology for extending the life of 193-nm immersion lithography. It is the most useful techniques of advancing downscaling in semiconductors and can theoretically be used scale infinitely down. For the self-aligned type of double patterning, such as self-aligned double patterning (SADP), self-aligned triple patterning (SATP), and self-aligned quadruple patterning (SAQP)[1], we have reported that spacer-pattern processing is more difficult than line-pattern processing since the former includes more fluctuating factors, and that improving the performance of the core pattern is essential to solving this problem. Similarly, as calls for even more improvement in line edge roughness (LER) have come to be made, we have investigated the relationship between the core pattern and LER. Thus, given the importance of finding a means of securing pattern fidelity in the core pattern to improve critical dimension uniformity (CDU) and LER, we improved resist contrast resulting in dramatically reduced LER and improved spacer CD uniformity over the wafer surface. This paper presents the results of observing pattern fidelity in the double patterning process from many aspects and the results of testing a technique for high-accuracy management of pattern fidelity.
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Hidetami Yaegashi, Hidetami Yaegashi, Kenichi Oyama, Kenichi Oyama, Arisa Hara, Arisa Hara, Sakurako Natori, Sakurako Natori, Shohei Yamauchi, Shohei Yamauchi, Masatoshi Yamato, Masatoshi Yamato, "Sustainable scaling technique on double-patterning process", Proc. SPIE 8682, Advances in Resist Materials and Processing Technology XXX, 868204 (29 March 2013); doi: 10.1117/12.2011359; https://doi.org/10.1117/12.2011359


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