Solving the issue of line edge/width roughness (LER/LWR) in chip manufacturing is becoming increasingly urgent as the feature size continues to decrease. Several post-lithography processing techniques have been investigated by the semiconductor industry, but they were often proved to be inadequate in one area or another. In this study, a near isotropic ion implantation process, called Plasma Ribbon Beam Technology, was tuned for photoresist treatment and used to reduce LER/LWR by >30% while minimizing loss in the critical dimension (CD). Different implantation chemistries were evaluated and process parameters including energy, angle, beam current, and dose, were optimized. The LER/LWR measurement was performed on an SEM system designed for CD metrology. SEM images with resist lines of 3μm long were taken to capture more low frequency data. The results showed that, with Ar implantation on 193/193i photoresists, a 27-37% before-etch reduction in LER/LWR was achieved on 65nm and 45nm half-pitch lines whereas the CD change was controlled under ±1%. Preliminary test results on EUV photoresists have demonstrated similar trend. Compared to untreated photoresist, the LER/LWR power spectral density (PSD) data showed more than a half decade improvement in both the mid-frequency and low-frequency range. The significant low-frequency improvement affords this technique a unique advantage over other competing approaches. Pattern transfer of the LER/LWR improvements has been successfully demonstrated on 193/193i resists using both inorganic and organic ARC (anti-reflective coating).