29 March 2013 20nm VIA BEOL patterning challenges
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Higher density on 20nm logic chips require tighter pitches to be implemented not only at critical metal layers, but at BEOL critical VIA layers as well. Smaller pitches on critical via are no longer achievable through the conventional positive tone development (PTD) process. Instead, negative tone development (NTD) is considered, evaluated, and integrated as an alternative, along with the double patterning (DP) method. Additionally, preliminary results on NTD+DP patterning challenges, including patterning verification, are presented in this paper.
© (2013) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Chien-Hsien S. Lee, Chien-Hsien S. Lee, Sohan Singh Mehta, Sohan Singh Mehta, Wontae Hwang, Wontae Hwang, Hui Husan Tsai, Hui Husan Tsai, Michael Anderson, Michael Anderson, Yayi Wei, Yayi Wei, Matthew Herrick, Matthew Herrick, Xiang Hu, Xiang Hu, Bumhwan Jeon, Bumhwan Jeon, Shyam Pal, Shyam Pal, } "20nm VIA BEOL patterning challenges", Proc. SPIE 8682, Advances in Resist Materials and Processing Technology XXX, 86820D (29 March 2013); doi: 10.1117/12.2011843; https://doi.org/10.1117/12.2011843

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