29 March 2013 Capability study and challenges to sub-2x nm node contact hole patterning
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Abstract
As the scaling down of design rule for high density memory device continues, the contact hole size shrinkage becomes one of the major challenges to patterning. Many shrinkage approaches have been introduced after litho. process, such as chemical shrink, PR reflow, RIE shrink, etc. However, CD uniformity control for these shrink processes is critical, and minimum pitch size is still dominated by the resolution limitation of lithography tools. In this paper, we adopt SADP (self-aligned double patterning) process combined with additional non-critical mask step to form 32nm hp elliptical single row dense and isolated contact holes. The CD uniformity is well controlled by SADP process, and chip size reduction is achievable by this high-density single row layout compared with interlace contact hole design. We also compared this new approach with chemical shrink process, and both the CD uniformity and resolution limit are improved. With optimized step-by-step etch process, we have successfully demonstrated the contact hole patterns on full-structure substrate. For the future application toward sub-2x nm node, this approach is also expectable with mature SADP process.
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Wan-Lin Kuo, Wan-Lin Kuo, Ya-Ting Chan, Ya-Ting Chan, Meng-Feng Tsai, Meng-Feng Tsai, Yi-Shiang Chang, Yi-Shiang Chang, Chia-Chi Lin, Chia-Chi Lin, Ming-Chien Chiu, Ming-Chien Chiu, Chun-Hsun Chen, Chun-Hsun Chen, Hung-Ming Wu, Hung-Ming Wu, Mao-Hsing Chiu, Mao-Hsing Chiu, } "Capability study and challenges to sub-2x nm node contact hole patterning", Proc. SPIE 8682, Advances in Resist Materials and Processing Technology XXX, 86821G (29 March 2013); doi: 10.1117/12.2011434; https://doi.org/10.1117/12.2011434
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