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12 April 2013 Computational aspects of optical lithography extension by directed self-assembly
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EUV insertion timing for High Volume Manufacturing is still an uncertainty due to source power and EUV mask infrastructure limitations. Directed Self Assembly (DSA) processes offer the promise of providing alternative ways to extend optical lithography cost-effectively for use in the 10nm node and beyond. The goal of this paper is to look into the technical prospect of DSA technology, particularly in the computational and DFM area. We have developed a prototype computational patterning toolset in-house to enable an early Design –Technology Co-Optimization to study the feasibility of using DSA in patterning semiconductor devices and circuits. From this toolset we can identify the set of DSA specific design restrictions specific to a DSA process and plan to develop a novel full chip capable computational patterning solution with DSA. We discuss the DSA Computational Lithography (CL) infrastructure using the via and fin layers as examples. Early wafer data is collected from the DSA testmask that was built using these new toolsets. Finally we discuss the DSA ecosystem requirements for enabling DSA lithography and propose how EDA vendors can play a role in making DSA Lithography (DSAL) a full-chip viable technology for multiple process layers.
© (2013) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Kafai Lai, Chi-chun Liu, Jed Pitera, Daniel J. Dechene, Anthony Schepis, Jassem Abdallah, Hsinyu Tsai, Mike Guillorn, Joy Cheng, Gregory Doerk, Melia Tjio, Charles Rettner, Olalekan Odesanya, Melih Ozlem, and Neal Lafferty "Computational aspects of optical lithography extension by directed self-assembly", Proc. SPIE 8683, Optical Microlithography XXVI, 868304 (12 April 2013);

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