12 April 2013 Inverse lithography technique for advanced CMOS nodes
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Resolution Enhancement Techniques have continuously improved over the last decade, driven by the ever growing constraints of lithography process. Despite the large number of RET applied, some hotspot configurations remain challenging for advanced nodes due to aggressive design rules. Inverse Lithography Technique (ILT) is evaluated here as a substitute to the dense OPC baseline. Indeed ILT has been known for several years for its near-to-ideal mask quality, while also being potentially more time consuming in terms of OPC run and mask processing. We chose to evaluate Mentor Graphics’ ILT engine “pxOPCTM” on both lines and via hotspot configurations. These hotspots were extracted from real 28nm test cases where the dense OPC solution is not satisfactory. For both layer types, the reference OPC consists of a dense OPC engine coupled to rule-based and/or model-based assist generation method. The same CM1 model is used for the reference and the ILT OPC. ILT quality improvement is presented through Optical Rule Check (ORC) results with various adequate detectors. Several mask manufacturing rule constraints (MRC) are considered for the ILT solution and their impact on process ability is checked after mask processing. A hybrid OPC approach allowing localized ILT usage is presented in order to optimize both quality and runtime. A real mask is prepared and fabricated with this method. Finally, results analyzed on silicon are presented to compare localized ILT to reference dense OPC.
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Alexandre Villaret, Alexandre Villaret, Alexander Tritchkov, Alexander Tritchkov, Jorge Entradas, Jorge Entradas, Emek Yesilada, Emek Yesilada, } "Inverse lithography technique for advanced CMOS nodes", Proc. SPIE 8683, Optical Microlithography XXVI, 86830E (12 April 2013); doi: 10.1117/12.2010111; https://doi.org/10.1117/12.2010111


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