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12 April 2013 Wafer topography modeling for ionic implantation mask correction dedicated to 2x nm FDSOI technologies
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Reflection by wafer topography and underlying layers during optical lithography can cause unwanted exposure in the resist [1]. This wafer stack effect phenomenon which is neglected for larger nodes than 45nm, is becoming problematic for 32nm technology node and below at the ionic implantation process. This phenomenon is expected to be attenuated by the use of anti-reflecting coating but increases process complexity and adds cost and cycle time penalty. As a consequence, an OPC based solution is today under evaluation to cope with stack effects involved in ionic implantation patterning [2] [3]. For the source drain (SD) ionic implantation process step on 28nm Fully Depleted Silicon-on-Insulator (FDSOI) technology, active silicon areas, poly silicon patterns, Shallow Trench Isolation (STI), Silicon-on-Insulator (SOI) areas and the transitions between these different regions result in significant SD implant pattern critical dimension variations. The large number of stack variations involved in these effects implies a complex modeling to simulate pattern degradations. This paper deals with the characterization of stack effects on 28nm node using SOI substrates. The large number of measurements allows to highlight all individual and combined stack effects. A new modeling flow has been developed in order to generate wafer stack aware OPC model. The accuracy and the prediction of the model is presented in this paper.
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Jean-Christophe Michel, Jean-Christophe Le Denmat, Elodie Sungauer, Frédéric Robert, Emek Yesilada, Ana-Maria Armeanu, Jorge Entradas, John L. Sturtevant, Thuy Do, and Yuri Granik "Wafer topography modeling for ionic implantation mask correction dedicated to 2x nm FDSOI technologies", Proc. SPIE 8683, Optical Microlithography XXVI, 86830I (12 April 2013);


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