12 April 2013 3D resist profile full chip verification and hot spot disposition
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Abstract
For 28 nm technology node and below resist profiles need to be taken in to consideration during optical proximity correction (OPC) and verification. The low k1 results in a shallower depth of focus and thus thinner resists, which combined with the process limits increases the risk of resist degradation. Only considering the resist critical dimensions at a single focal plane (such as at the bottom of the resist stack) will miss the impact of the resist 3D profile, like top loss or bottom footing, which can transfer to etch hard pattern failures. To date, modeling to study resist 3D profiles has been available using rigorous simulators and has been used as a verification method for hot spots captured during full chip OPC verification, but not for full chip verification due to the high computational run time cost. This paper demonstrates a 3D resist compact OPC model concept and implementation in a full chip OPC and verification flow. The results show significant improvement for full chip OPC quality with a good correlation between simulation and real wafer hot spots. Because resist profiles are not directly correlated to etch failure, the relationship between the resist profile and etch failures and how to characterize the threshold to dispose the hot spots for the 3D compact model was also investigated.
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Qing Yang, Qing Yang, ShyueFong Quek, ShyueFong Quek, YeeMei Foong, YeeMei Foong, Jens Hassmann, Jens Hassmann, DongQing Zhang, DongQing Zhang, Andre Leschok, Andre Leschok, Tang Yun, Tang Yun, Mu Feng, Mu Feng, Stanislas Baron, Stanislas Baron, JianHong Qiu, JianHong Qiu, Taksh Pandey, Taksh Pandey, Bo Yan, Bo Yan, Russell Dover, Russell Dover, } "3D resist profile full chip verification and hot spot disposition", Proc. SPIE 8683, Optical Microlithography XXVI, 86831N (12 April 2013); doi: 10.1117/12.2010595; https://doi.org/10.1117/12.2010595
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