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Self-aligned double patterning friendly configuration for standard cell library considering placement impact
Pattern matching for identifying and resolving non-decomposition-friendly designs for double patterning technology (DPT)
Detailed routing with advanced flexibility and in compliance with self-aligned double patterning constraints
Pioneering an on-the-fly simulation technique for the detection of layout-dependent effects during IC design phase
Compact modeling of fin-width roughness induced FinFET device variability using the perturbation method
Post-routing back-end-of-line layout optimization for improved time-dependent dielectric breakdown reliability