29 March 2013 Pioneering an on-the-fly simulation technique for the detection of layout-dependent effects during IC design phase
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Abstract
As semiconductor manufacturing migrates to more advanced technology nodes, the performance improvement anticipated from scaling has failed to match expectations. This failure is due to the emergence of layout-dependent effects (LDEs) not encountered in the design flow prior 65nm process node. We propose a novel methodology that allows the early detection of LDEs during schematic creation. Different from all previous works, this methodology accurately calculates LDEs by interfacing interactively with a simulator tool. Our research indicates that no previous works suggested the use of “on-the-fly” simulation, using Eldo Interactive, to study LDEs. In fact, the use of Calibre tools [2] has been suggested to help the designer check certain basic electrical constraints (like matching) under the existence of LDEs, by specifying the matching condition as a comment added to the original Pyxis schematic netlist. [1] These comments are then transformed into verification rules that are added and checked by Calibre. The proposed flow is tested on a 40nm OTA design, with results not only as accurate as those previously obtained from post-layout analysis, but also equal to or better speed of execution, demonstrating the practicality of using “on-the-fly” simulation to detect and resolve LDEs early in the design flow.
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Amr M. S. Tossen, Ahmed Ramadan, Rami Fathy Salem, "Pioneering an on-the-fly simulation technique for the detection of layout-dependent effects during IC design phase", Proc. SPIE 8684, Design for Manufacturability through Design-Process Integration VII, 86840B (29 March 2013); doi: 10.1117/12.2009242; https://doi.org/10.1117/12.2009242
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