Rethinking ASIC design with next generation lithography and process integration

Kaushik Vaidyanathan; Renzhi Liu; Lars Liebmann; Kafai Lai; Andrzej Strojwas; Larry Pileggi

doi:10.1117/12.2014374

29 March 2013 Rethinking ASIC design with next generation lithography and process integration

Kaushik Vaidyanathan; Renzhi Liu; Lars Liebmann; Kafai Lai; Andrzej Strojwas; Larry Pileggi

Author Affiliations +

Proceedings Volume 8684, Design for Manufacturability through Design-Process Integration VII; 86840C (2013) https://doi.org/10.1117/12.2014374
Event: SPIE Advanced Lithography, 2013, San Jose, California, United States

Abstract

Given the deployment delays for EUV, several next generation lithography (NGL) options are being actively researched. Several cost-effective NGL solutions, such as self-aligned double patterning through sidewall image transfer (SIT) and directed self-assembly (DSA), in conjunction with process integration challenges, mandate grating-like pattern design. As part of the GRATEdd project, we have evaluated the design cost of grating-based design for ASICs (application specific ICs). Based on our observations we have engineered fundamental changes to the primary ASIC design components to make scaling affordable and useful in deeply scaled sub-20 nm technologies: unidirectional-M1 based standard cells, application-specific smart SRAM synthesis, and statistical and self-healing analog design.

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Kaushik Vaidyanathan, Kaushik Vaidyanathan, Renzhi Liu, Renzhi Liu, Lars Liebmann, Lars Liebmann, Kafai Lai, Kafai Lai, Andrzej Strojwas, Andrzej Strojwas, Larry Pileggi, Larry Pileggi, } "Rethinking ASIC design with next generation lithography and process integration", Proc. SPIE 8684, Design for Manufacturability through Design-Process Integration VII, 86840C (29 March 2013); doi: 10.1117/12.2014374; https://doi.org/10.1117/12.2014374

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