29 March 2013 Triple patterning lithography (TPL) layout decomposition using end-cutting
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Triple patterning lithography (TPL) is one of the most promising techniques in the 14nm logic node and beyond. However, traditional LELELE type TPL technology suffers from native conflict and overlapping problems. Recently LELEEC process was proposed to overcome the limitations, where the third mask is used to generate the end-cuts. In this paper we propose the first study for LELEEC layout decomposition. Conflict graphs and end- cut graphs are constructed to extract all the geometrical relationships of input layout and end-cut candidates. Based on these graphs, integer linear programming (ILP) is formulated to minimize the con ict number and the stitch number.
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Bei Yu, Bei Yu, Jhih-Rong Gao, Jhih-Rong Gao, David Z. Pan, David Z. Pan, } "Triple patterning lithography (TPL) layout decomposition using end-cutting", Proc. SPIE 8684, Design for Manufacturability through Design-Process Integration VII, 86840G (29 March 2013); doi: 10.1117/12.2011355; https://doi.org/10.1117/12.2011355


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