29 March 2013 Double patterning with dual hard mask for 28nm node devices and below
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Abstract
In this paper, we report a double patterning process resulting in amorphous silicon (a-Si) gate lines with a thickness of 80nm and a lateral critical dimension (CD) below 30nm. We present a full stack for a double patterning approach for etch transfer down to a Si layer, including a hard mask in which the line and cut patterning are performed. The importance of the hard mask (HM) in the success or failure of the exercise is evidenced. Once the suitable HM has been selected, the etch chemistry is shown to have a significant impact on the line width roughness (LWR) of the gate. Ultimately, remarkably low LWR could be achieved on gates exhibiting straight profile. All the results shown in this paper have been obtained on 300mm wafers.
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Hubert Hody, Hubert Hody, Vasile Paraschiv, Vasile Paraschiv, Emma Vecchio, Emma Vecchio, Sabrina Locorotondo, Sabrina Locorotondo, Gustaf Winroth, Gustaf Winroth, Raja Athimulam, Raja Athimulam, Werner Boullart, Werner Boullart, } "Double patterning with dual hard mask for 28nm node devices and below", Proc. SPIE 8685, Advanced Etch Technology for Nanopatterning II, 86850P (29 March 2013); doi: 10.1117/12.2010951; https://doi.org/10.1117/12.2010951
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