31 May 2013 FPGA implementation of a software-defined radar processor
Author Affiliations +
A unified digital pulse compression processor is introduced as a radar-application-specific-processor (RASP) architecture for the next generation of adaptive radar. Based on traditional pulse compression matched filter and correlation receiver, the processor integrates specific designs to handle waveform diversities, which includes random noise waveforms, as well as digital transceiver self-reconfiguration for adaptive radars. Initial prototype of this processor is implemented with the latest Xilinx FPGA device and tested with an RF spaceborne radar transceiver testbed. Initial validation results show the effectiveness of real-time processing and engineering concepts.
© (2013) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Hernan Suarez, Hernan Suarez, Yan Rockee Zhang, Yan Rockee Zhang, "FPGA implementation of a software-defined radar processor", Proc. SPIE 8714, Radar Sensor Technology XVII, 871403 (31 May 2013); doi: 10.1117/12.2016034; https://doi.org/10.1117/12.2016034


Back to Top