28 January 2013 A novel 3D algorithm for VLSI floorplanning
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Proceedings Volume 8760, International Conference on Communication and Electronics System Design; 87601S (2013) https://doi.org/10.1117/12.2012334
Event: International Conference on Communication and Electronics System Design, 2013, Jaipur, India
Abstract
3-D VLSI circuit is becoming a hot issue because of its potential of enhancing performance, while it is also facing challenges such as the increased complexity on floorplanning and placement in VLSI Physical design. Efficient 3-D floorplan representations are needed to handle the placement optimization in new circuit designs. We analyze and categorize some state-of-the-art 3-D representations, and propose a Ternary tree model for 3-D nonslicing floorplans, extending the B*tree from 2D.This paper proposes a novel optimization algorithm for packing of 3D rectangular blocks. The new techniques considered are Differential evolutionary algorithm (DE) is very fast in that it evaluates the feasibility of a Ternary tree representation. Experimental results based on MCNC benchmark with constraints show that our proposed Differential Evolutionary (DE) can quickly produce optimal solutions.
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D. Gracia Nirmala Rani, S. Rajaram, Athira Sudarasan, "A novel 3D algorithm for VLSI floorplanning", Proc. SPIE 8760, International Conference on Communication and Electronics System Design, 87601S (28 January 2013); doi: 10.1117/12.2012334; https://doi.org/10.1117/12.2012334
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