14 March 2013 Floorplanning with boundary constraints by using AE-TCG
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Proceedings Volume 8768, International Conference on Graphic and Image Processing (ICGIP 2012); 87681V (2013) https://doi.org/10.1117/12.2010850
Event: 2012 International Conference on Graphic and Image Processing, 2012, Singapore, Singapore
Abstract
It is practical and crucial that a designer will want to control the positions of some modules along the chip boundary in the final packing for I/O connection. To solve the problem we propose an algorithm named Area Estimate Transitive Closure Graphs (AE-TCG). By analyzing the feasible condition of boundary constraints, AE-TCG guarantees that the result of each perturbation is a feasible placement with boundary constraints, and doesn’t need to transform the infeasible solution to feasible one. Unlike most of the previous algorithms getting the target area after packing, AE-TCG can satisfy the boundary constraints and estimate the area of feasible placement without packing after random perturbation, then accept the beneficial perturbation. For the property of concentrate itself, AE-TCG is running without Simulated Annealing (SA) process. The experimental results show that AE-TCG is effective and efficient than other algorithms with boundary constraints in commonly used MCNC benchmark circuits.
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YiMing Li, MingTian Zhou, Yi Li, "Floorplanning with boundary constraints by using AE-TCG", Proc. SPIE 8768, International Conference on Graphic and Image Processing (ICGIP 2012), 87681V (14 March 2013); doi: 10.1117/12.2010850; https://doi.org/10.1117/12.2010850
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