20 March 2013 DSP code optimization based on cache
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Proceedings Volume 8768, International Conference on Graphic and Image Processing (ICGIP 2012); 87682Q (2013) https://doi.org/10.1117/12.2010893
Event: 2012 International Conference on Graphic and Image Processing, 2012, Singapore, Singapore
Abstract
DSP program‟s running efficiency on board is often lower than which via the software simulation during the program development, which is mainly resulted from the user‟s improper use and incomplete understanding of the cache-based memory. This paper took the TI TMS320C6455 DSP as an example, analyzed its two-level internal cache, and summarized the methods of code optimization. Processor can achieve its best performance when using these code optimization methods. At last, a specific algorithm application in radar signal processing is proposed. Experiment result shows that these optimization are efficient.
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Chengfa Xu, Chengfa Xu, Chengcheng Li, Chengcheng Li, Bin Tang, Bin Tang, } "DSP code optimization based on cache", Proc. SPIE 8768, International Conference on Graphic and Image Processing (ICGIP 2012), 87682Q (20 March 2013); doi: 10.1117/12.2010893; https://doi.org/10.1117/12.2010893
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