14 March 2013 Implement of time division multiplexing high speed programmable Viterbi decoder IP core
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Proceedings Volume 8768, International Conference on Graphic and Image Processing (ICGIP 2012); 87685U (2013) https://doi.org/10.1117/12.2012476
Event: 2012 International Conference on Graphic and Image Processing, 2012, Singapore, Singapore
Abstract
The programmable Time Division multiplexing high Viterbi decoder IP core is studied in this paper. According to the characteristics of multiple communication system, the method of programmable time-division multiplexing is puts forward, the high-performance and less resource occupy IP core is designed. Based on SMIC 0.18um CMOS technology, the ASIC of IP core is test. The test results show that the IP core areas, power and frequency could satisfy demand of real-time communication.
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Lan Wu, Lan Wu, Qiliang Chen, Qiliang Chen, } "Implement of time division multiplexing high speed programmable Viterbi decoder IP core", Proc. SPIE 8768, International Conference on Graphic and Image Processing (ICGIP 2012), 87685U (14 March 2013); doi: 10.1117/12.2012476; https://doi.org/10.1117/12.2012476
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