14 March 2013 A multiphase clock generation based on DLL for source synchronous receiver in 65nm CMOS technology
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Proceedings Volume 8768, International Conference on Graphic and Image Processing (ICGIP 2012); 87686H (2013) https://doi.org/10.1117/12.2006152
Event: 2012 International Conference on Graphic and Image Processing, 2012, Singapore, Singapore
Abstract
This paper presents a multiphase clock generation circuit (MPCG) using delay locked loop (DLL). In order to achieve process independence, fixed bandwidth to operating frequency ratio, broad tuning range, and low jitter, the DLL design is based on self-biased technique augmented with jitter attenuation technique, which can achieve precise delay equal to the input reference clock period. Simulated in 65nm CMOS technology, the MPCG achieves an operating frequency range of 1.8GHz to 4GHz. And the MPCG will generate eight clocks evenly spaced by 45 degrees. At 2.5GHz, its peak to peak jitter with quiescent supply is 10ps, and its power consumption is 11mW.
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Zhentao Li, Zhentao Li, Ziqiang Wang, Ziqiang Wang, Chen Jia, Chen Jia, Ke Huang, Ke Huang, Chun Zhang, Chun Zhang, Xuqiang Zheng, Xuqiang Zheng, Zhihua Wang, Zhihua Wang, } "A multiphase clock generation based on DLL for source synchronous receiver in 65nm CMOS technology", Proc. SPIE 8768, International Conference on Graphic and Image Processing (ICGIP 2012), 87686H (14 March 2013); doi: 10.1117/12.2006152; https://doi.org/10.1117/12.2006152
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