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14 March 2013 A design of 12-bit full differential successive approximation ADC
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Proceedings Volume 8768, International Conference on Graphic and Image Processing (ICGIP 2012); 87686W (2013) https://doi.org/10.1117/12.2008288
Event: 2012 International Conference on Graphic and Image Processing, 2012, Singapore, Singapore
Abstract
A 12-bit full differential successive approximation anolog-to-digital convertor (SAR ADC) with low power dissipation is proposed in this paper. The comparator is a crucial part in SAR ADC, and its accuracy, speed and offset have an effect on the performance of ADC. In this paper, a multi-stage comparator is designed, which is composed of three stage amplifiers and a latch,and the offset calibration technique is applied, too. The DAC consists of 64 unit capacitors. The circuit is designed under TSMC CMOS 0.18μmrf process. The simulation results show that under a 3.3V power supply, the performance of SNDR reaches nearly 71.25dB and the SFDR reaches nearly 80.97dB with the condition that the sampling frequency is 0.67MHz. The power consumption of SAR is about 4.5mW.
© (2013) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Wei Gao, Lei Zhang, Xinghua Wang, Mu Yao, and Peng Gao "A design of 12-bit full differential successive approximation ADC", Proc. SPIE 8768, International Conference on Graphic and Image Processing (ICGIP 2012), 87686W (14 March 2013); https://doi.org/10.1117/12.2008288
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