24 January 2013 Optimal design of phase change random access memory based on 130nm CMOS technology
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Proceedings Volume 8782, 2012 International Workshop on Information Storage and Ninth International Symposium on Optical Storage; 87820F (2013) https://doi.org/10.1117/12.2016907
Event: 2012 International Workshop on Information Data Storage and Ninth International Symposium on Optical Storage, 2012, Shanghai, China
Abstract
An 8Mb phase change random access memory (PCRAM) has been developed by a 130nm 4-ML standard CMOS technology based on the Resistor-on-Via-stacked-Plug (RVP) storage cell structure. This phase change resistor is formed after CMOS logic fabrication. PCRAM can be embedded without changing any logic device and process. The memory cell selector is implemented by a standard 1.2V NMOS device. Aimed at the resistance distributions, lowering the operation current and improving the bit yield, some methods are used to optimize the design of the chip.
© (2013) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Daolin Cai, Daolin Cai, Houpeng Chen, Houpeng Chen, Qian Wang, Qian Wang, Xiao Hong, Xiao Hong, Yifeng Chen, Yifeng Chen, Linhai Xu, Linhai Xu, Xi Li, Xi Li, Zhaomin Wang, Zhaomin Wang, Yiyun Zhang, Yiyun Zhang, Zhitang Song, Zhitang Song, } "Optimal design of phase change random access memory based on 130nm CMOS technology", Proc. SPIE 8782, 2012 International Workshop on Information Storage and Ninth International Symposium on Optical Storage, 87820F (24 January 2013); doi: 10.1117/12.2016907; https://doi.org/10.1117/12.2016907
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