24 January 2013 16-Kbit SPI phase change memory chip with ECC scheme
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Proceedings Volume 8782, 2012 International Workshop on Information Storage and Ninth International Symposium on Optical Storage; 87820G (2013) https://doi.org/10.1117/12.2018644
Event: 2012 International Workshop on Information Data Storage and Ninth International Symposium on Optical Storage, 2012, Shanghai, China
Abstract
A serial peripheral interface (SPI) 16-Kbit phase change memory chip based on 0.13μm CMOS process is designed. It contains a parallel error correcting code (ECC) circuit, which can correct 2 bits in every 8 bits without clock delay, enabling the write and read operations performed at bus speed. All the data transfers in 8-bit groups and can be read or written with write protection scheme by unlimited cycle, in which address can automatically increase one by one. Simulation results show that the chip can work correctly in SPI mode and with ECC scheme. It is now under testing.
© (2013) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Yiyun Zhang, Yiyun Zhang, Houpeng Chen, Houpeng Chen, Zhitang Song, Zhitang Song, Xi Li, Xi Li, Xiao Hong, Xiao Hong, Qian Wang, Qian Wang, Rong Jin, Rong Jin, Zhaomin Wang, Zhaomin Wang, Daolin Cai, Daolin Cai, "16-Kbit SPI phase change memory chip with ECC scheme", Proc. SPIE 8782, 2012 International Workshop on Information Storage and Ninth International Symposium on Optical Storage, 87820G (24 January 2013); doi: 10.1117/12.2018644; https://doi.org/10.1117/12.2018644
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