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13 May 2013 Sub-nanometer in-die overlay metrology: measurement and simulation at the edge of finiteness
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The target size reduction for overlay metrology is driven by the optimization of the device area. Furthermore, for the future semiconductor nodes accurate metrology on the order of 0.2 nm is necessary locally in the device area, requiring small in-die targets that fit within the product structures on the wafer. In this, the diffraction-based overlay metrology using optical scatterometry is challenged to extreme limits. The small grating cannot be considered as an infinitely repeating line-space structure with a sharply peaked spectrum, however a continuous spectrum is observed. Also, metrology proximity effects due to the environment near the metrology target need to be taken into account. On the one hand, this sets strict design and assembly rules of the metrology sensor. On the other hand, the optical ray-based analysis is extended to wave-based analysis to capture the full extent of the overlay application and sensor. In this publication, the challenges of sub-nanometer in-die overlay metrology are addressed, including measurements and simulations.
© (2013) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Henk-Jan H. Smilde, Martin Jak, Arie den Boef, Mark van Schijndel, Murat Bozkurt, Andreas Fuchs, Maurits van der Schaar, Steffen Meyer, Stephen Morgan, Kaustuve Bhattacharyya, Guo-Tsai Huang, Chih-Ming Ke, and Kai-Hsiung Chen "Sub-nanometer in-die overlay metrology: measurement and simulation at the edge of finiteness", Proc. SPIE 8788, Optical Measurement Systems for Industrial Inspection VIII, 87881N (13 May 2013);

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