Overlay metrology for stacked layers will be playing a key role in bringing 3D IC devices into manufacturing. However, such bonded wafer pairs present a metrology challenge for optical microscopy tools by the opaque nature of silicon. Using infrared microscopy, silicon wafers become transparent to the near-infrared (NIR) wavelengths of the electromagnetic spectrum, enabling metrology at the interface of bonded wafer pairs.
Wafers can be bonded face to face (F2F) or face to back (F2B) which the stacking direction is dictated by how the stacks are carried in the process and functionality required. For example, Memory stacks tend to use F2B stacking enables a better managed design. Current commercial tools use single image technique for F2F bonding overlay measurement because depth of focus is sufficient to include both surfaces; and use multiple image techniques for F2B overlay measurement application for the depth of focus is no longer sufficient to include both stacked wafer surfaces. There is a need to specify the Z coordinate or stacking wafer number through the silicon when visiting measurement wafer sites. Two shown images are of the same (X, Y) but separate Z location acquired at focus position of each wafer surface containing overlay marks. Usually the top surface image is bright and clear; however, the bottom surface image is somewhat darker and noisier as an adhesive layer is used in between to bond the silicon wafers. Thus the top and bottom surface images are further processed to achieve similar brightness and noise level before merged for overlay measurement.
This paper presents a special overlay measurement technique, using the infrared differential interference contrast (DIC) microscopy technique to measure the F2B wafer bonding overlay by a single shot image. A pair of thinned wafers at 50 and 150 μm thickness is bonded on top of a carrier wafer to evaluate the bonding overlay. It works on the principle of interferometry to gain information about the optical path length of the stacked wafers, to enhance the image contrast of overlay marks features even though they are locating in different Z plane. A two dimensional mirror-symmetric overlay marks for both top and bottom processing wafers is designed and printed in each die in order to know and realize the best achievable wafer to wafer bonding processing. A self-developed analysis algorithms is used to identify the overlay error between the stacking wafers and the interconnect structures. The experimental overlay results after wafer bonding including inter-die and intra-die analysis results will be report in the full paper. Correlation of overlay alignment offset data to electrical yield, provides an early indication of bonded wafer yield.