High-Speed Serial Shift Registers

John X. Przybysz; R. D. Blaugher

doi:10.1117/12.943982

18 May 1988 High-Speed Serial Shift Registers

John X. Przybysz, R. D. Blaugher

Proceedings Volume 0879, Sensing, Discrimination, and Signal Processing and Superconducting Materials and Intrumentation; (1988) https://doi.org/10.1117/12.943982
Event: 1988 Los Angeles Symposium: O-E/LASE '88, 1988, Los Angeles, CA, United States

Abstract

An integrated circuit chip was designed for a Josephson based shift register, and chip processing was initiated. The circuit design simulates operation at 25 GHz in the SPICE program. The transmission lines used to distribute the three-phase clock were modeled with the SUPERCOMPACT program to provide balanced, in-phase circuit drive, up to 10 GHz. Integrated circuit processing procedures have been developed to permit reactive ion etching of all seven deposited layers. The 6.25 mm square chip featured a twelve-gate, four-stage shift register fabricated with Nb/A10x/Nb Josephson junctions of 2000 A/cm critical current density.

Citation Download Citation

John X. Przybysz and R. D. Blaugher "High-Speed Serial Shift Registers", Proc. SPIE 0879, Sensing, Discrimination, and Signal Processing and Superconducting Materials and Intrumentation, (18 May 1988); https://doi.org/10.1117/12.943982

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