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26 September 2013 Nanostencil lithography for fabrication of III-V nanostructures
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Abstract
Nanostencil Lithography (NStL), while comparatively still in infant stages, is proving to be a viable option for low-cost and high resolution fabrication. An ideal stencil for NStL consists of a low-stressed silicon nitride membrane supported on a silicon chip with required patterned features in nanometer range that become apertures. The stencil is used as a shadow mask and placed in close contact on top of a substrate/wafer. This pair is then ready for either depositing metal through the apertures in the stencil using variety of deposition techniques or etching the substrate using dry etching techniques with stencil acting as a mask. The nanostencils were fabricated using focused ion beam writing on a silicon nitride window/membrane. We made well-ordered array of 700 nm diameter and 15 nm thick gold and chromium nanodots on III-V substrate. Metal layers were deposited using e-beam evaporator. The formed gold nanodots can be used for vapor-liquid-solid nanowire growth (bottom-up), while the chromium nanodots were used as a mask for reactive ion etching of GaAs structures, for instance, fabricating nanowires (top-down approach). We used the nanostencil directly as a mask for dry etching of InP substrate for making nanoholes array. Making these types of nanoholes in silicon oxide layer deposited on the top of III-V substrate opens the possibility to use in selective area growth of nanowires. Additionally, we fabricated optical nanoantenna structures to demonstrate other possible usage of NStL.
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Kaushal Vora, Fouad Karouta, and Chennupati Jagadish "Nanostencil lithography for fabrication of III-V nanostructures", Proc. SPIE 8816, Nanoengineering: Fabrication, Properties, Optics, and Devices X, 88161B (26 September 2013); https://doi.org/10.1117/12.2022609
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