19 July 2013 Experiences on developing digital down conversion algorithms using Xilinx system generator
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Proceedings Volume 8878, Fifth International Conference on Digital Image Processing (ICDIP 2013); 887840 (2013) https://doi.org/10.1117/12.2030640
Event: Fifth International Conference on Digital Image Processing, 2013, Beijing, China
Abstract
The Digital Down Conversion (DDC) algorithm is a classical signal processing method which is widely used in radar and communication systems. In this paper, the DDC function is implemented by Xilinx System Generator tool on FPGA. System Generator is an FPGA design tool provided by Xilinx Inc and MathWorks Inc. It is very convenient for programmers to manipulate the design and debug the function, especially for the complex algorithm. Through the developing process of DDC function based on System Generator, the results show that System Generator is a very fast and efficient tool for FPGA design.
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Chengfa Xu, Yuan Yuan, Lizhi Zhao, "Experiences on developing digital down conversion algorithms using Xilinx system generator", Proc. SPIE 8878, Fifth International Conference on Digital Image Processing (ICDIP 2013), 887840 (19 July 2013); doi: 10.1117/12.2030640; https://doi.org/10.1117/12.2030640
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