Line edge roughness (LER) or line width roughness (LWR) is a fundamental challenge in the semiconductor industry.
LWR on transistor gate length is a dominant parameter for determining the variability of threshold voltage, on-current
and off-current, and LER on interconnect impacts breakdown voltages. Integrated circuit (IC) scaling enabled by
lithography is the technology to increase device density and improve performance. However, scaling below 32nn
technology node induces short-channel effect (SCE) because of the short distance between the transistor source and the
drain. Final LER on the working layer results from several processes, and, thus, LER controls rely on lithography, resist
properties, post-resist-development processing, pattern transfer methods, and photomask LER. Now, pattern generation
is main source of LER, where short exposure wavelength and consecutive low photon numbers result in discrete photon
flux and shot noise, causing high LER. Extreme ultraviolet lithography (EUVL) uses shorter wavelengths and a lower
dose than the current 193 nm lithography, making LWR one of the three most critical challenges. Characterization of
LER is also a challenge. The current rms method is broadly used; however, this approach is not enough and a better
method has yet to be established.