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16 September 2013 In-die mask registration for multi-patterning
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Abstract
193nm immersion lithography is the mainstream production technology for the 20nm and 14nm logic nodes. Considering multi-patterning as the technology to solve the very low k1 situation in the resolution equation puts extreme pressure on the intra-field overlay, to which mask registration error is a major error contributor. The International Technology Roadmap for Semiconductors (ITRS) requests a registration error below 4 nm for each mask of a multi-patterning set forming one layer on the wafer. For mask metrology at the 20nm and 14nm logic nodes, maintaining a precision-to-tolerance (P/T) ratio below 0.25 will be very challenging. Mask registration error impacts intra-field wafer overlay directly and has a major impact on wafer yield. We will discuss a solution to support full in-die registration metrology on reticles.
© (2013) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
F. Laske, S. Kunitani, T. Kamibayashi, M. Yamana, A. Fuse, M. Wagner, K.-D. Roeth, M. Ferber, M. Daneshpanah, S. Czerkas, and H. Sakaguchi "In-die mask registration for multi-patterning", Proc. SPIE 8880, Photomask Technology 2013, 888024 (16 September 2013); https://doi.org/10.1117/12.2027200
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