Paper
1 October 2013 Imaging challenges in 20nm and 14nm logic nodes: hot spots performance in Metal1 layer
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Proceedings Volume 8886, 29th European Mask and Lithography Conference; 88860N (2013) https://doi.org/10.1117/12.2030968
Event: 29th European Mask and Lithography Conference, 2013, Dresden, Germany
Abstract
The 20nm Metal1 layer, based on ARM standard cells, has a 2D design with minimum pitch of 64nm. This 2D design requires a Litho-Etch-Litho-Etch (LELE) double patterning. The whole design is divided in 2 splits: Me1A and Me1B. But solution of splitting conflicts needs stitching at some locations, what requires good Critical Dimension (CD) and overlay control to provide reliable contact between 2 stitched line ends. ASML Immersion NXT tools are aimed at 20 and 14nm logic production nodes. Focus control requirements become tighter, as existing 20nm production logic layouts, based on ARM, have about 50-60nm focus latitude and tight CD Uniformity (CDU) specifications, especially for line ends. IMEC inspected 20nm production Metal1 ARM standard cells with a Negative Tone Development (NTD) process using the Process Window Qualification-like technique experimentally and by Brion Tachyon LMC by simulations. Stronger defects were found thru process variations. A calibrated Tachyon model proved a good overall predictability capability for this process. Selected defects are likely to be transferred to hard mask during etch. Further, CDU inspection was performed for these critical features. Hot spots showed worse CD uniformity than specifications. Intra-field CDU contribution is significant in overall CDU budget, where reticle has major impact due to high MEEF of hot spots. Tip-to-Tip and tip-to-line hot spots have high MEEF and its variation over the field. Best focus variation range was determined by best focus offsets between hot spots and its variation within the field.
© (2013) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
V. Timoshkov, D. Rio, H. Liu, W. Gillijns, J. Wang, P. Wong, D. Van Den Heuvel, V. Wiaux, P. Nikolsky, and J. Finders "Imaging challenges in 20nm and 14nm logic nodes: hot spots performance in Metal1 layer", Proc. SPIE 8886, 29th European Mask and Lithography Conference, 88860N (1 October 2013); https://doi.org/10.1117/12.2030968
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Cited by 2 scholarly publications and 4 patents.
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KEYWORDS
Reticles

Critical dimension metrology

Semiconducting wafers

Logic

Tolerancing

Double patterning technology

Metals

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